Port map association in VHDL - Mini Project: Build & Apply

Port Map Association in VHDL

📖 Scenario: You are designing a simple digital circuit in VHDL. You have a component called AndGate that takes two input signals and produces one output signal. You want to connect this component inside a top-level entity using port map association.

🎯 Goal: Build a VHDL design that instantiates the AndGate component inside a top-level entity called TopLevel using port map association to connect signals.

📋 What You'll Learn

Create a component declaration for AndGate with ports A, B as inputs and Y as output.

Declare signals sigA, sigB, and sigY in the architecture.

Instantiate the AndGate component inside the architecture using port map association with signals connected to ports.

Print the VHDL code that shows the complete top-level entity with component instantiation.

💡 Why This Matters

🌍 Real World

Port map association is used in hardware design to connect components inside larger circuits, just like plugging cables between devices.

💼 Career

Understanding port map association is essential for FPGA and ASIC designers who write VHDL code to build digital hardware.

1

Create the top-level entity and architecture with signals

Write a VHDL entity called TopLevel with no ports. Inside the architecture Behavior, declare signals sigA, sigB, and sigY all of type std_logic.

VHDL

entity TopLevel is
end TopLevel;

architecture Behavior of TopLevel is
    -- Declare signals here

begin

end Behavior;

Hint

Remember to declare signals inside the architecture declaration section before begin.

2

Declare the AndGate component

Inside the architecture Behavior of TopLevel, declare a component called AndGate with ports: A and B as in std_logic, and Y as out std_logic.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TopLevel is
end TopLevel;

architecture Behavior of TopLevel is
    signal sigA : std_logic;
    signal sigB : std_logic;
    signal sigY : std_logic;

    -- Declare AndGate component here

begin

end Behavior;

Hint

Component declaration goes inside the architecture declaration section before begin.

3

Instantiate the AndGate component using port map association

Inside the architecture Behavior of TopLevel, instantiate the AndGate component with label U1. Use port map association to connect sigA to A, sigB to B, and sigY to Y.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TopLevel is
end TopLevel;

architecture Behavior of TopLevel is
    signal sigA : std_logic;
    signal sigB : std_logic;
    signal sigY : std_logic;

    component AndGate is
        port(
            A : in std_logic;
            B : in std_logic;
            Y : out std_logic
        );
    end component;

begin
    -- Instantiate AndGate component U1 here

end Behavior;

Hint

Use the syntax Label : ComponentName port map(port => signal, ...); inside the architecture body.

4

Display the complete VHDL code

Write a VHDL print statement or comment that shows the complete TopLevel entity and architecture code including the component declaration and instantiation.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TopLevel is
end TopLevel;

architecture Behavior of TopLevel is
    signal sigA : std_logic;
    signal sigB : std_logic;
    signal sigY : std_logic;

    component AndGate is
        port(
            A : in std_logic;
            B : in std_logic;
            Y : out std_logic
        );
    end component;

begin
    U1 : AndGate port map(
        A => sigA,
        B => sigB,
        Y => sigY
    );

-- Your code here to display or comment the complete code
end Behavior;

Hint

You can add a comment showing the complete code or print it if your environment supports it.

Practice

1. What is the main purpose of port map in VHDL?

easy

A. To connect component ports to signals in the design

B. To declare new signals inside an architecture

C. To define the behavior of a component

D. To specify timing constraints for signals

Solution

1. Step 1: Understand the role of port map

   Port map is used to link the ports of a component to signals in the surrounding design.

2. Step 2: Differentiate from other VHDL constructs

   Declaring signals, defining behavior, or timing constraints are done elsewhere, not with port map.

3. Final Answer:

   To connect component ports to signals in the design -> Option A

4. Quick Check:

   Port map = connect ports to signals [OK]

Hint: Port map always links ports to signals by name [OK]

Common Mistakes:

• Confusing port map with signal declaration
• Thinking port map defines component behavior
• Mixing port map with timing constraints

2. Which of the following is the correct syntax for named port map association in VHDL?

easy

A. U1: component_name port map (clk : clk_signal, rst : reset_signal);

B. U1: component_name map port (clk = clk_signal, rst = reset_signal);

C. U1: component_name port map (clk => clk_signal, rst => reset_signal);

D. U1: component_name port map (clk <- clk_signal, rst <- reset_signal);

Solution

1. Step 1: Recall named association syntax

   Named port map uses the format port_name => signal_name inside parentheses.

2. Step 2: Check each option

   U1: component_name port map (clk => clk_signal, rst => reset_signal); uses => correctly. The other options use incorrect symbols (=, :, <-) for association.

3. Final Answer:

   U1: component_name port map (clk => clk_signal, rst => reset_signal); -> Option C

4. Quick Check:

   Named port map uses => [OK]

Hint: Use => for named port mapping in VHDL [OK]

Common Mistakes:

• Using = instead of => in port map
• Using : or <- instead of =>
• Omitting parentheses around port map list

3. Given the component declaration:

component AND_GATE
port(
  A : in std_logic;
  B : in std_logic;
  Y : out std_logic
);
end component;

And the following port map:

U1: AND_GATE port map (A => sig1, B => sig2, Y => out_sig);

What signal is connected to port B?

medium

A. sig1

B. B

C. out_sig

D. sig2

Solution

1. Step 1: Identify port map association for B

   In the port map, B is connected to sig2 as shown by B => sig2.

2. Step 2: Confirm signal connected to port B

   The signal connected to port B is sig2, not sig1 or out_sig.

3. Final Answer:

   sig2 -> Option D

4. Quick Check:

   Port B connected to sig2 [OK]

Hint: Match port name on left with signal on right in port map [OK]

Common Mistakes:

• Confusing port names with signal names
• Assuming order matters instead of names
• Selecting output signal instead of input

4. Identify the error in the following port map:

U2: MY_COMPONENT port map (clk => clock, reset => rst, data_in => input_data, data_out = output_data);

medium

A. Using '=' instead of '=>' for data_out association

B. Missing semicolon at the end of port map

C. Port names and signals are reversed

D. Component instance name 'U2' is invalid

Solution

1. Step 1: Check each port association syntax

   All associations use '=>' except data_out which uses '=' incorrectly.

2. Step 2: Verify other syntax elements

   Semicolon is present, port names and signals are correctly ordered, and instance name is valid.

3. Final Answer:

   Using '=' instead of '=>' for data_out association -> Option A

4. Quick Check:

   Port map uses =>, not = [OK]

Hint: All port associations must use =>, never = [OK]

Common Mistakes:

• Using = instead of => in one or more ports
• Confusing signal and port order
• Forgetting semicolon at end (not in this case)

5. You have a component with ports clk, rst, in_data, and out_data. You want to connect it to signals clk_sig, reset_sig, data_bus, and result_bus respectively. Which port map correctly associates these signals by name?

hard

A. U3: COMP port map (clk_sig => clk, reset_sig => rst, data_bus => in_data, result_bus => out_data);

B. U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus);

C. U3: COMP port map (clk => reset_sig, rst => clk_sig, in_data => result_bus, out_data => data_bus);

D. U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => result_bus, out_data => data_bus);

Solution

1. Step 1: Match each port to its correct signal

   Ports clk, rst, in_data, out_data must connect to clk_sig, reset_sig, data_bus, result_bus respectively.

2. Step 2: Check each option's mapping

   U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus); correctly maps each port to its matching signal. The other options swap signals incorrectly.

3. Final Answer:

   U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus); -> Option B

4. Quick Check:

   Port to signal mapping must be exact [OK]

Hint: Port name on left, signal on right in port map [OK]

Common Mistakes:

• Swapping signal names in port map
• Reversing port and signal positions
• Mixing input and output signals