Port map association in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of port map with positional association

Consider the following VHDL entity and architecture. What is the output on Y after the port map instantiation?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AND_GATE is
  Port ( A : in STD_LOGIC;
         B : in STD_LOGIC;
         Y : out STD_LOGIC);
end AND_GATE;

architecture Behavioral of AND_GATE is
begin
  Y <= A and B;
end Behavioral;

entity TOP is
  Port ( X1 : in STD_LOGIC;
         X2 : in STD_LOGIC;
         Z : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  signal S : STD_LOGIC;
begin
  U1: entity work.AND_GATE port map(X1, X2, S);
  Z <= S;
end Structural;

A Z outputs '0' regardless of inputs

B Z outputs '1' only if both X1 and X2 are '1'

C Z outputs '1' if either X1 or X2 is '1'

D Z outputs '1' only if X1 is '1' regardless of X2

💡 Hint

Remember that the AND gate outputs '1' only when both inputs are '1'. Positional port map matches ports in order.

The port map uses positional association: X1 connects to A, X2 to B, and S to Y. The AND gate outputs '1' only if both inputs are '1', so Z follows that logic.

❓ Predict Output

intermediate

Output of port map with named association

Given the following VHDL code, what is the value of Z when X1='0' and X2='1'?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity OR_GATE is
  Port ( A : in STD_LOGIC;
         B : in STD_LOGIC;
         Y : out STD_LOGIC);
end OR_GATE;

architecture Behavioral of OR_GATE is
begin
  Y <= A or B;
end Behavioral;

entity TOP is
  Port ( X1 : in STD_LOGIC;
         X2 : in STD_LOGIC;
         Z : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  signal S : STD_LOGIC;
begin
  U1: entity work.OR_GATE port map(B => X1, A => X2, Y => S);
  Z <= S;
end Structural;

A Z = '0'

B Z = 'Z' (high impedance)

C Z = '1'

D Z = 'X' (unknown)

💡 Hint

Check how named association connects signals to ports regardless of order.

Named association connects B to X1 ('0') and A to X2 ('1'). The OR gate outputs '1' if either input is '1', so Z is '1'.

🔧 Debug

advanced

Identify the error in port map association

What error will occur when compiling the following VHDL code?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity NOT_GATE is
  Port ( A : in STD_LOGIC;
         Y : out STD_LOGIC);
end NOT_GATE;

architecture Behavioral of NOT_GATE is
begin
  Y <= not A;
end Behavioral;

entity TOP is
  Port ( X : in STD_LOGIC;
         Z : out STD_LOGIC);
end TOP;

architecture Structural of TOP is
  signal S : STD_LOGIC;
begin
  U1: entity work.NOT_GATE port map(A => X, B => S);
  Z <= S;
end Structural;

A Compilation error: port 'B' does not exist in NOT_GATE

B Runtime error: signal 'S' not initialized

C No error, code compiles and runs correctly

D Compilation error: missing port map for output 'Y'

💡 Hint

Check the port names in the entity and the port map association.

The NOT_GATE entity has ports A and Y. The port map tries to connect a non-existent port B, causing a compilation error.

📝 Syntax

advanced

Syntax error in port map association

Which option contains the correct syntax for port map association in VHDL?

A U1: entity work.MY_ENTITY port map(A => X, B => Y);

B U1: entity work.MY_ENTITY port map(A = X, B = Y);

C U1: entity work.MY_ENTITY port map(A -> X, B -> Y);

D U1: entity work.MY_ENTITY port map(A : X, B : Y);

💡 Hint

Remember the correct symbol for named association in port maps.

In VHDL, named association uses the => symbol inside port map. Other symbols cause syntax errors.

🚀 Application

expert

Number of signals connected in complex port map

Given the following VHDL code snippet, how many signals are connected to the component ports after the port map?

VHDL

entity COMPLEX_COMP is
  Port (
    CLK : in STD_LOGIC;
    RST : in STD_LOGIC;
    DATA_IN : in STD_LOGIC_VECTOR(3 downto 0);
    DATA_OUT : out STD_LOGIC_VECTOR(3 downto 0);
    READY : out STD_LOGIC
  );
end COMPLEX_COMP;

architecture Behavioral of COMPLEX_COMP is
begin
  -- Implementation
end Behavioral;

entity TOP is
  Port (
    CLK_TOP : in STD_LOGIC;
    RST_TOP : in STD_LOGIC;
    IN_TOP : in STD_LOGIC_VECTOR(3 downto 0);
    OUT_TOP : out STD_LOGIC_VECTOR(3 downto 0);
    READY_TOP : out STD_LOGIC
  );
end TOP;

architecture Structural of TOP is
  signal internal_ready : STD_LOGIC;
begin
  U1: entity work.COMPLEX_COMP port map(
    CLK => CLK_TOP,
    RST => RST_TOP,
    DATA_IN => IN_TOP,
    DATA_OUT => OUT_TOP,
    READY => internal_ready
  );
  READY_TOP <= internal_ready;
end Structural;

A 3 signals connected

B 4 signals connected

C 6 signals connected

D 5 signals connected

💡 Hint

Count each port in the component and check how many signals are connected in the port map.

The component COMPLEX_COMP has 5 ports: CLK, RST, DATA_IN, DATA_OUT, READY. All are connected to signals in the port map, so 5 signals are connected.

Practice

1. What is the main purpose of port map in VHDL?

easy

A. To connect component ports to signals in the design

B. To declare new signals inside an architecture

C. To define the behavior of a component

D. To specify timing constraints for signals

Solution

1. Step 1: Understand the role of port map

   Port map is used to link the ports of a component to signals in the surrounding design.

2. Step 2: Differentiate from other VHDL constructs

   Declaring signals, defining behavior, or timing constraints are done elsewhere, not with port map.

3. Final Answer:

   To connect component ports to signals in the design -> Option A

4. Quick Check:

   Port map = connect ports to signals [OK]

Hint: Port map always links ports to signals by name [OK]

Common Mistakes:

• Confusing port map with signal declaration
• Thinking port map defines component behavior
• Mixing port map with timing constraints

2. Which of the following is the correct syntax for named port map association in VHDL?

easy

A. U1: component_name port map (clk : clk_signal, rst : reset_signal);

B. U1: component_name map port (clk = clk_signal, rst = reset_signal);

C. U1: component_name port map (clk => clk_signal, rst => reset_signal);

D. U1: component_name port map (clk <- clk_signal, rst <- reset_signal);

Solution

1. Step 1: Recall named association syntax

   Named port map uses the format port_name => signal_name inside parentheses.

2. Step 2: Check each option

   U1: component_name port map (clk => clk_signal, rst => reset_signal); uses => correctly. The other options use incorrect symbols (=, :, <-) for association.

3. Final Answer:

   U1: component_name port map (clk => clk_signal, rst => reset_signal); -> Option C

4. Quick Check:

   Named port map uses => [OK]

Hint: Use => for named port mapping in VHDL [OK]

Common Mistakes:

• Using = instead of => in port map
• Using : or <- instead of =>
• Omitting parentheses around port map list

3. Given the component declaration:

component AND_GATE
port(
  A : in std_logic;
  B : in std_logic;
  Y : out std_logic
);
end component;

And the following port map:

U1: AND_GATE port map (A => sig1, B => sig2, Y => out_sig);

What signal is connected to port B?

medium

A. sig1

B. B

C. out_sig

D. sig2

Solution

1. Step 1: Identify port map association for B

   In the port map, B is connected to sig2 as shown by B => sig2.

2. Step 2: Confirm signal connected to port B

   The signal connected to port B is sig2, not sig1 or out_sig.

3. Final Answer:

   sig2 -> Option D

4. Quick Check:

   Port B connected to sig2 [OK]

Hint: Match port name on left with signal on right in port map [OK]

Common Mistakes:

• Confusing port names with signal names
• Assuming order matters instead of names
• Selecting output signal instead of input

4. Identify the error in the following port map:

U2: MY_COMPONENT port map (clk => clock, reset => rst, data_in => input_data, data_out = output_data);

medium

A. Using '=' instead of '=>' for data_out association

B. Missing semicolon at the end of port map

C. Port names and signals are reversed

D. Component instance name 'U2' is invalid

Solution

1. Step 1: Check each port association syntax

   All associations use '=>' except data_out which uses '=' incorrectly.

2. Step 2: Verify other syntax elements

   Semicolon is present, port names and signals are correctly ordered, and instance name is valid.

3. Final Answer:

   Using '=' instead of '=>' for data_out association -> Option A

4. Quick Check:

   Port map uses =>, not = [OK]

Hint: All port associations must use =>, never = [OK]

Common Mistakes:

• Using = instead of => in one or more ports
• Confusing signal and port order
• Forgetting semicolon at end (not in this case)

5. You have a component with ports clk, rst, in_data, and out_data. You want to connect it to signals clk_sig, reset_sig, data_bus, and result_bus respectively. Which port map correctly associates these signals by name?

hard

A. U3: COMP port map (clk_sig => clk, reset_sig => rst, data_bus => in_data, result_bus => out_data);

B. U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus);

C. U3: COMP port map (clk => reset_sig, rst => clk_sig, in_data => result_bus, out_data => data_bus);

D. U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => result_bus, out_data => data_bus);

Solution

1. Step 1: Match each port to its correct signal

   Ports clk, rst, in_data, out_data must connect to clk_sig, reset_sig, data_bus, result_bus respectively.

2. Step 2: Check each option's mapping

   U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus); correctly maps each port to its matching signal. The other options swap signals incorrectly.

3. Final Answer:

   U3: COMP port map (clk => clk_sig, rst => reset_sig, in_data => data_bus, out_data => result_bus); -> Option B

4. Quick Check:

   Port to signal mapping must be exact [OK]

Hint: Port name on left, signal on right in port map [OK]

Common Mistakes:

• Swapping signal names in port map
• Reversing port and signal positions
• Mixing input and output signals