FIFO full and empty flags in VHDL - Mini Project: Build & Apply

FIFO full and empty flags

📖 Scenario: You are designing a simple FIFO (First-In-First-Out) buffer in VHDL for a hardware project. The FIFO needs to tell when it is full and when it is empty using two flags.

🎯 Goal: Build a VHDL code that creates a FIFO with signals to indicate when it is full and when it is empty.

📋 What You'll Learn

Create signals for read and write pointers

Create signals for full and empty flags

Implement logic to update full and empty flags based on pointers

Print the status of full and empty flags

💡 Why This Matters

🌍 Real World

FIFO buffers are used in hardware designs to manage data flow between components running at different speeds.

💼 Career

Understanding FIFO full and empty flags is essential for hardware engineers working on digital design and FPGA programming.

1

Create FIFO pointer signals

Create two signals called write_ptr and read_ptr of type integer range 0 to 3 to represent the write and read pointers of a FIFO with depth 4.

VHDL

-- Your code here

Hint

Use signal keyword and specify the range 0 to 3 for both pointers.

2

Create full and empty flag signals

Create two signals called full and empty of type std_logic to represent the FIFO full and empty flags.

VHDL

signal write_ptr : integer range 0 to 3 := 0;
signal read_ptr : integer range 0 to 3 := 0;
-- Your code here

Hint

Initialize full to '0' and empty to '1' because FIFO starts empty.

3

Implement logic for full and empty flags

Write VHDL code that sets full to '1' when write_ptr is one less than read_ptr modulo 4, and sets empty to '1' when write_ptr equals read_ptr. Use a process sensitive to write_ptr and read_ptr.

VHDL

signal write_ptr : integer range 0 to 3 := 0;
signal read_ptr : integer range 0 to 3 := 0;
signal full : std_logic := '0';
signal empty : std_logic := '1';

-- Your code here

Hint

Use modulo 4 arithmetic to wrap pointers and compare for full condition.

4

Display full and empty flags

Write a simple process that prints the values of full and empty flags using report statements.

VHDL

signal write_ptr : integer range 0 to 3 := 0;
signal read_ptr : integer range 0 to 3 := 0;
signal full : std_logic := '0';
signal empty : std_logic := '1';

process(write_ptr, read_ptr) is
begin
    if (write_ptr = (read_ptr + 3) mod 4) then
        full <= '1';
    else
        full <= '0';
    end if;

    if (write_ptr = read_ptr) then
        empty <= '1';
    else
        empty <= '0';
    end if;
end process;

-- Your code here

Hint

Use report to print the flag values and std_logic'image to convert them to strings.

Practice

1. What does the FIFO full flag indicate in a VHDL design?

easy

A. The buffer is partially filled

B. The buffer is empty and has no data to read

C. The buffer is being reset

D. The buffer is full and cannot accept more data

Solution

1. Step 1: Understand FIFO full flag meaning

   The FIFO full flag signals when the buffer has reached its maximum capacity.

2. Step 2: Interpret the flag's implication

   When full, no more data can be written safely to the FIFO.

3. Final Answer:

   The buffer is full and cannot accept more data -> Option D

4. Quick Check:

   FIFO full flag = buffer full [OK]

Hint: Full flag means no more writes allowed [OK]

Common Mistakes:

• Confusing full flag with empty flag
• Thinking full means partially filled
• Assuming full flag resets the buffer

2. Which VHDL signal type is most appropriate for FIFO full and empty flags?

easy

A. std_logic

B. integer

C. real

D. string

Solution

1. Step 1: Identify flag signal requirements

   Flags represent binary states: high or low (1 or 0).

2. Step 2: Choose suitable VHDL type

   std_logic is used for single-bit signals representing logic levels.

3. Final Answer:

   std_logic -> Option A

4. Quick Check:

   Flags use std_logic type [OK]

Hint: Flags are single-bit signals, use std_logic [OK]

Common Mistakes:

• Using integer or real for binary flags
• Using string type for flags
• Confusing std_logic_vector with std_logic

3. Given this VHDL snippet for a FIFO full flag:

full_flag <= '1' when (write_ptr + 1) mod depth = read_ptr else '0';

What does this expression check?

medium

A. If the write pointer equals the read pointer, indicating empty

B. If the next write position equals the read position, indicating full

C. If the FIFO is partially full

D. If the FIFO is being reset

Solution

1. Step 1: Analyze the condition

   The expression checks if incrementing write_ptr wraps to read_ptr.

2. Step 2: Understand FIFO full logic

   When next write position equals read pointer, FIFO is full to avoid overwrite.

3. Final Answer:

   If the next write position equals the read position, indicating full -> Option B

4. Quick Check:

   Next write = read pointer means full [OK]

Hint: Full when next write equals read pointer [OK]

Common Mistakes:

• Confusing full condition with empty condition
• Ignoring modulo wrap-around
• Assuming write_ptr = read_ptr means full

4. Identify the error in this FIFO empty flag assignment:

empty_flag <= '1' when write_ptr = read_ptr + 1 else '0';

medium

A. The write_ptr and read_ptr should be swapped

B. The flag should be std_logic_vector, not std_logic

C. The condition should be write_ptr = read_ptr for empty

D. The else part should assign '1' instead of '0'

Solution

1. Step 1: Recall FIFO empty condition

   FIFO is empty when write_ptr equals read_ptr, no data to read.

2. Step 2: Compare given condition

   The condition uses write_ptr = read_ptr + 1, which is incorrect for empty.

3. Final Answer:

   The condition should be write_ptr = read_ptr for empty -> Option C

4. Quick Check:

   Empty flag triggers when pointers are equal [OK]

Hint: Empty when write_ptr equals read_ptr [OK]

Common Mistakes:

• Using offset in empty condition
• Confusing full and empty pointer conditions
• Incorrect flag signal type

5. You have a FIFO with depth 8, write_ptr = 7, read_ptr = 6.
Using this full flag logic:

full_flag <= '1' when (write_ptr + 1) mod 8 = read_ptr else '0';

What is the value of full_flag?

hard

A. '0', FIFO is not full

B. '1', FIFO is full

C. Undefined, pointers out of range

D. '0', FIFO is empty

Solution

1. Step 1: Calculate (write_ptr + 1) mod depth

   (7 + 1) mod 8 = 8 mod 8 = 0.

2. Step 2: Compare with read_ptr

   read_ptr = 6, so 0 != 6, condition false, full_flag = '0'.

3. Final Answer:

   '0', FIFO is not full -> Option A

4. Quick Check:

   Next write pointer != read pointer means not full [OK]

Hint: Calculate (write_ptr+1) mod depth carefully [OK]

Common Mistakes:

• Forgetting modulo wrap-around
• Assuming full when pointers differ
• Mixing up read and write pointers