FIFO full and empty flags in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of the FIFO full flag logic?

Consider a FIFO with a write pointer (wr_ptr) and a read pointer (rd_ptr) both 3 bits wide. The full flag is set when the write pointer is one position behind the read pointer in a circular buffer of size 8.

Given the following VHDL snippet, what is the value of full when wr_ptr = "110" and rd_ptr = "111"?

VHDL

signal wr_ptr : std_logic_vector(2 downto 0) := "110";
signal rd_ptr : std_logic_vector(2 downto 0) := "111";
signal full : std_logic;

full <= '1' when (wr_ptr = rd_ptr - 1) else '0';

A '1'

B Undefined behavior

C Signal assignment error

D '0'

💡 Hint

Remember that subtraction on std_logic_vector is not directly supported. Consider how the pointers wrap around in a circular buffer.

The expression wr_ptr = rd_ptr - 1 is invalid because std_logic_vector does not support direct arithmetic operations. This causes a signal assignment error. Logically, if it worked, "111" (7) - 1 = 6 ("110"), so full would be '1', but the code will not compile.

❓ Predict Output

intermediate

What is the empty flag output for given pointers?

In a FIFO design, the empty flag is set when the write pointer equals the read pointer.

Given the following VHDL code snippet, what is the value of empty when wr_ptr = "001" and rd_ptr = "001"?

VHDL

signal wr_ptr : std_logic_vector(2 downto 0) := "001";
signal rd_ptr : std_logic_vector(2 downto 0) := "001";
signal empty : std_logic;

empty <= '1' when wr_ptr = rd_ptr else '0';

A Undefined behavior

B '0'

C Signal assignment error

D '1'

💡 Hint

Check if the pointers are equal.

The empty flag is '1' when the write and read pointers are equal, indicating the FIFO is empty. Here both pointers are "001", so empty is '1'.

🔧 Debug

advanced

Identify the error in FIFO full flag logic

Examine the following VHDL code snippet for the FIFO full flag. Identify the error that will cause incorrect full flag behavior.

VHDL

signal wr_ptr : unsigned(2 downto 0);
signal rd_ptr : unsigned(2 downto 0);
signal full : std_logic;

full <= '1' when wr_ptr = rd_ptr - 1 else '0';

A The full flag logic is correct and will work as intended.

B The pointers are unsigned, so subtraction is invalid and causes a syntax error.

C The full flag should be set when wr_ptr equals rd_ptr, not rd_ptr - 1.

D The subtraction does not handle wrap-around correctly, causing full to never be set.

💡 Hint

Think about how pointer subtraction works in a circular buffer.

The full flag logic is correct and will work as intended. Unsigned subtraction in VHDL (from numeric_std) performs modulo 2^N arithmetic, which handles the circular wrap-around perfectly for power-of-two FIFO sizes. For rd_ptr = "000", rd_ptr - 1 = "111", correctly setting full when wr_ptr = "111".

📝 Syntax

advanced

Which option causes a syntax error in FIFO empty flag assignment?

Given the FIFO empty flag logic, which of the following VHDL assignments will cause a syntax error?

A empty <= '1' when wr_ptr == rd_ptr else '0';

B empty <= '1' when (wr_ptr = rd_ptr) else '0';

C empty <= '1' when wr_ptr = rd_ptr else '0';

D empty <= '1' when wr_ptr /= rd_ptr else '0';

💡 Hint

Check the equality operator syntax in VHDL.

In VHDL, the equality operator is =, not ==. Option A uses ==, which causes a syntax error.

🚀 Application

expert

Calculate the number of items in FIFO given pointers and flags

A FIFO has 8 slots (3-bit pointers). The write pointer is at "101" (decimal 5), and the read pointer is at "011" (decimal 3). The FIFO full flag is '0' and empty flag is '0'.

How many items are currently stored in the FIFO?

A 6

B 2

C 5

D 3

💡 Hint

Calculate the difference between write and read pointers modulo FIFO size.

The number of items in the FIFO is (unsigned(wr_ptr) - unsigned(rd_ptr)) mod 8 = (5 - 3) mod 8 = 2. The flags being '0' confirm it's neither empty (wr_ptr == rd_ptr) nor full (wr_ptr == rd_ptr - 1 mod 8).

Practice

1. What does the FIFO full flag indicate in a VHDL design?

easy

A. The buffer is partially filled

B. The buffer is empty and has no data to read

C. The buffer is being reset

D. The buffer is full and cannot accept more data

Solution

1. Step 1: Understand FIFO full flag meaning

   The FIFO full flag signals when the buffer has reached its maximum capacity.

2. Step 2: Interpret the flag's implication

   When full, no more data can be written safely to the FIFO.

3. Final Answer:

   The buffer is full and cannot accept more data -> Option D

4. Quick Check:

   FIFO full flag = buffer full [OK]

Hint: Full flag means no more writes allowed [OK]

Common Mistakes:

• Confusing full flag with empty flag
• Thinking full means partially filled
• Assuming full flag resets the buffer

2. Which VHDL signal type is most appropriate for FIFO full and empty flags?

easy

A. std_logic

B. integer

C. real

D. string

Solution

1. Step 1: Identify flag signal requirements

   Flags represent binary states: high or low (1 or 0).

2. Step 2: Choose suitable VHDL type

   std_logic is used for single-bit signals representing logic levels.

3. Final Answer:

   std_logic -> Option A

4. Quick Check:

   Flags use std_logic type [OK]

Hint: Flags are single-bit signals, use std_logic [OK]

Common Mistakes:

• Using integer or real for binary flags
• Using string type for flags
• Confusing std_logic_vector with std_logic

3. Given this VHDL snippet for a FIFO full flag:

full_flag <= '1' when (write_ptr + 1) mod depth = read_ptr else '0';

What does this expression check?

medium

A. If the write pointer equals the read pointer, indicating empty

B. If the next write position equals the read position, indicating full

C. If the FIFO is partially full

D. If the FIFO is being reset

Solution

1. Step 1: Analyze the condition

   The expression checks if incrementing write_ptr wraps to read_ptr.

2. Step 2: Understand FIFO full logic

   When next write position equals read pointer, FIFO is full to avoid overwrite.

3. Final Answer:

   If the next write position equals the read position, indicating full -> Option B

4. Quick Check:

   Next write = read pointer means full [OK]

Hint: Full when next write equals read pointer [OK]

Common Mistakes:

• Confusing full condition with empty condition
• Ignoring modulo wrap-around
• Assuming write_ptr = read_ptr means full

4. Identify the error in this FIFO empty flag assignment:

empty_flag <= '1' when write_ptr = read_ptr + 1 else '0';

medium

A. The write_ptr and read_ptr should be swapped

B. The flag should be std_logic_vector, not std_logic

C. The condition should be write_ptr = read_ptr for empty

D. The else part should assign '1' instead of '0'

Solution

1. Step 1: Recall FIFO empty condition

   FIFO is empty when write_ptr equals read_ptr, no data to read.

2. Step 2: Compare given condition

   The condition uses write_ptr = read_ptr + 1, which is incorrect for empty.

3. Final Answer:

   The condition should be write_ptr = read_ptr for empty -> Option C

4. Quick Check:

   Empty flag triggers when pointers are equal [OK]

Hint: Empty when write_ptr equals read_ptr [OK]

Common Mistakes:

• Using offset in empty condition
• Confusing full and empty pointer conditions
• Incorrect flag signal type

5. You have a FIFO with depth 8, write_ptr = 7, read_ptr = 6.
Using this full flag logic:

full_flag <= '1' when (write_ptr + 1) mod 8 = read_ptr else '0';

What is the value of full_flag?

hard

A. '0', FIFO is not full

B. '1', FIFO is full

C. Undefined, pointers out of range

D. '0', FIFO is empty

Solution

1. Step 1: Calculate (write_ptr + 1) mod depth

   (7 + 1) mod 8 = 8 mod 8 = 0.

2. Step 2: Compare with read_ptr

   read_ptr = 6, so 0 != 6, condition false, full_flag = '0'.

3. Final Answer:

   '0', FIFO is not full -> Option A

4. Quick Check:

   Next write pointer != read pointer means not full [OK]

Hint: Calculate (write_ptr+1) mod depth carefully [OK]

Common Mistakes:

• Forgetting modulo wrap-around
• Assuming full when pointers differ
• Mixing up read and write pointers