Avoiding common synthesis pitfalls in VHDL - Mini Project: Build & Apply

Avoiding Common Synthesis Pitfalls in VHDL

📖 Scenario: You are designing a simple digital circuit using VHDL. Your goal is to write code that synthesizes correctly without common mistakes that cause synthesis tools to fail or produce unexpected hardware.

🎯 Goal: Build a VHDL process that counts from 0 to 7 using a 3-bit signal, avoiding common synthesis pitfalls such as inferred latches, incomplete sensitivity lists, and improper signal assignments.

📋 What You'll Learn

Create a 3-bit signal called counter initialized to 0

Create a clock signal called clk (assume it is declared)

Write a process triggered on the rising edge of clk

Inside the process, increment counter from 0 to 7 and wrap around to 0

Avoid incomplete sensitivity lists and inferred latches

Print the value of counter using a report statement

💡 Why This Matters

🌍 Real World

Digital designers write VHDL code to describe hardware circuits. Avoiding synthesis pitfalls ensures the code translates correctly to hardware without errors or unintended behavior.

💼 Career

Understanding synthesis pitfalls is essential for FPGA and ASIC engineers to produce reliable, synthesizable hardware designs.

1

DATA SETUP: Declare the counter signal

Declare a 3-bit signal called counter of type std_logic_vector(2 downto 0) and initialize it to "000".

VHDL

-- Declare the 3-bit signal counter initialized to "000"
signal counter : std_logic_vector(2 downto 0) := "000";

Hint

Use signal counter : std_logic_vector(2 downto 0) := "000"; to declare and initialize.

2

CONFIGURATION: Declare the clock signal clk

Declare a clock signal called clk of type std_logic and initialize it to '0'.

VHDL

signal counter : std_logic_vector(2 downto 0) := "000";
-- Declare the clock signal clk initialized to '0'
signal clk : std_logic := '0';

Hint

Use signal clk : std_logic := '0'; to declare the clock.

3

CORE LOGIC: Write a process to increment counter on rising edge of clk

Write a process with sensitivity list containing only clk. Inside, use if rising_edge(clk) then to increment counter by 1. When counter reaches "111", reset it to "000".

VHDL

signal counter : std_logic_vector(2 downto 0) := "000";
signal clk : std_logic := '0';

-- Write a process triggered on rising_edge(clk) to increment counter and wrap from "111" to "000"
process(clk)
begin
    -- Your code here
end process;

Hint

Use if rising_edge(clk) then and convert counter to unsigned to add 1, then back to std_logic_vector.

4

OUTPUT: Add a report statement to display counter value

Inside the process, after updating counter, add a report statement to print the current value of counter as a string.

VHDL

signal counter : std_logic_vector(2 downto 0) := "000";
signal clk : std_logic := '0';

process(clk)
begin
    if rising_edge(clk) then
        if counter = "111" then
            counter <= "000";
        else
            counter <= std_logic_vector(unsigned(counter) + 1);
        end if;
        -- Add a report statement to print counter
    end if;
end process;

Hint

Use report "Counter value: " & integer'image(to_integer(unsigned(counter))); to print the counter value.

Practice

1. Which practice helps avoid unintended latches in VHDL synthesis?

easy

A. Write combinational logic inside clocked processes

B. Use asynchronous resets only

C. Avoid using clock signals in processes

D. Assign all signals in every branch of a conditional statement

Solution

1. Step 1: Understand latch inference

   Unintended latches occur if signals are not assigned in all branches of a conditional, causing synthesis tools to infer memory elements.

2. Step 2: Assign signals in all branches

   By assigning signals in every branch, you ensure the signal always has a defined value, preventing latch inference.

3. Final Answer:

   Assign all signals in every branch of a conditional statement -> Option D

4. Quick Check:

   Complete signal assignment = no unintended latches [OK]

Hint: Always assign signals in all if-else branches to avoid latches [OK]

Common Mistakes:

• Leaving signals unassigned in some branches
• Using asynchronous resets incorrectly
• Mixing combinational and sequential logic improperly

2. Which of the following is the correct syntax for a synchronous process with a reset in VHDL?

easy

A. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

C. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

D. process(reset) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

Solution

1. Step 1: Check sensitivity list

   For synchronous reset, process sensitivity list includes only clock.

2. Step 2: Use nested if structure

   Clock edge first, then check reset inside for synchronous behavior.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; -> Option B

4. Quick Check:

   Reset inside clock edge = correct synchronous reset syntax [OK]

Hint: Sensitivity list only clk; nest reset inside rising_edge(clk) for synchronous reset [OK]

Common Mistakes:

• Including reset in sensitivity list (makes it asynchronous)
• Checking reset outside clock edge
• Using elsif instead of nested if

3. Given the following VHDL process, what will be the value of q after the rising edge of clk if reset is '0' and d is '1'?

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Previous value of q

Solution

1. Step 1: Check reset condition

   Reset is '0', so the reset branch is skipped.

2. Step 2: Check clock edge and assignment

   On rising edge of clk, q is assigned the value of d, which is '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Reset '0' + rising clk = q = d = '1' [OK]

Hint: If reset is '0', q follows d on clock edge [OK]

Common Mistakes:

• Confusing reset active level
• Assuming q keeps old value without clock edge
• Ignoring sensitivity list effects

4. Identify the synthesis issue in the following VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    end if;
end process;

medium

A. No issue; code is synthesizable as is

B. Syntax error due to missing sensitivity list signals

C. Unintended latch inferred because q is not assigned when enable = '0'

D. Process will not trigger on clock rising edge

Solution

1. Step 1: Analyze clocked process behavior

   In clocked processes, missing assignment in a branch implies hold previous value.

2. Step 2: Recognize standard template

   This is synthesizable as a flip-flop with enable; no latch inferred.

3. Final Answer:

   No issue; code is synthesizable as is -> Option A

4. Quick Check:

   Clocked process incomplete if = enabled FF hold [OK]

Hint: Incomplete assignments in clocked processes synthesize to enabled flip-flops [OK]

Common Mistakes:

• Confusing with combinational processes (which infer latches)
• Rewriting standard enabled FF template
• Mistaking intended hold for unintended latch

5. You want to design a synchronous counter with an active-high synchronous reset in VHDL. Which approach best avoids common synthesis pitfalls?

hard

A. Use a process with clock in sensitivity list; assign counter in all branches including reset and else

B. Use asynchronous reset only and assign counter only on clock rising edge

C. Assign counter only when reset is '0' and ignore other cases

D. Use combinational process without clock for counter increment

Solution

1. Step 1: Include only clock in sensitivity list

   For synchronous reset, only clock signal in process sensitivity list.

2. Step 2: Assign counter in all branches

   Assign counter to 0 on reset='1' and increment in else, all inside rising_edge(clk).

3. Final Answer:

   Use a process with clock in sensitivity list; assign counter in all branches including reset and else -> Option A

4. Quick Check:

   Synchronous reset + full assignments = safe synthesis [OK]

Hint: Always assign signals in all branches with clock in sensitivity list [OK]

Common Mistakes:

• Using asynchronous reset when synchronous is needed
• Missing assignments causing latches
• Using combinational logic for sequential counters