Avoiding common synthesis pitfalls in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output behavior of this VHDL process?

Consider the following VHDL process inside a synchronous design. What will be the value of q after the rising edge of clk if reset is '0' and d is '1'?

VHDL

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

A q will be '1' after the rising edge of clk

B q will be '0' after the rising edge of clk

C q will retain its previous value

D q will be undefined (X)

💡 Hint

Remember that reset is asynchronous and active high.

Since reset is '0', the reset condition is not active. On the rising edge of clk, q takes the value of d, which is '1'.

❓ Predict Output

intermediate

What error occurs with this combinational process?

Analyze the following VHDL process. What problem will synthesis tools report?

VHDL

process(a, b)
begin
  if a = '1' then
    y <= '1';
  end if;
end process;

A Syntax error due to missing else

B No error, y is fully assigned

C Latch inferred due to incomplete assignment of y

D Runtime error during simulation

💡 Hint

Think about what happens to y when a is not '1'.

Because y is assigned only when a is '1', synthesis infers a latch to hold the previous value when a is not '1'.

🔧 Debug

advanced

Identify the synthesis pitfall in this clocked process

Examine the following VHDL code snippet. What is the main synthesis issue?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    end if;
  end if;
end process;

A q may become a latch because it is not assigned when enable is '0'

B No issue, q is assigned correctly on clock edge

C Syntax error due to missing else clause

D q will be asynchronously reset

💡 Hint

Consider what happens to q when enable is '0' on clock edge.

In clocked processes, signals keep their value if not assigned. This is normal and does not infer latches.

📝 Syntax

advanced

Which option causes a syntax error in VHDL?

Identify the code snippet that will cause a syntax error during VHDL compilation.

A signal a : std_logic := '0';

B

entity my_entity is
  port(clk : in std_logic);
end my_entity;

C variable count : integer := 0;

D

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if
end process;

💡 Hint

Check for missing semicolons or keywords.

Option D is missing a semicolon after end if, causing a syntax error.

🚀 Application

expert

How many flip-flops are inferred by this VHDL code?

Given the following VHDL code, how many flip-flops will synthesis infer?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    q1 <= d1;
    if enable = '1' then
      q2 <= d2;
    end if;
  end if;
end process;

A 2 flip-flops

B 1 flip-flop

C 3 flip-flops

D No flip-flops, only latches

💡 Hint

Remember that signals assigned inside a clocked process infer flip-flops.

Both q1 and q2 are assigned on the rising edge of clk, so two flip-flops are inferred. The conditional assignment to q2 inside the clocked process does not cause latch inference.

Practice

1. Which practice helps avoid unintended latches in VHDL synthesis?

easy

A. Write combinational logic inside clocked processes

B. Use asynchronous resets only

C. Avoid using clock signals in processes

D. Assign all signals in every branch of a conditional statement

Solution

1. Step 1: Understand latch inference

   Unintended latches occur if signals are not assigned in all branches of a conditional, causing synthesis tools to infer memory elements.

2. Step 2: Assign signals in all branches

   By assigning signals in every branch, you ensure the signal always has a defined value, preventing latch inference.

3. Final Answer:

   Assign all signals in every branch of a conditional statement -> Option D

4. Quick Check:

   Complete signal assignment = no unintended latches [OK]

Hint: Always assign signals in all if-else branches to avoid latches [OK]

Common Mistakes:

• Leaving signals unassigned in some branches
• Using asynchronous resets incorrectly
• Mixing combinational and sequential logic improperly

2. Which of the following is the correct syntax for a synchronous process with a reset in VHDL?

easy

A. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

C. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

D. process(reset) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

Solution

1. Step 1: Check sensitivity list

   For synchronous reset, process sensitivity list includes only clock.

2. Step 2: Use nested if structure

   Clock edge first, then check reset inside for synchronous behavior.

3. Final Answer:

   process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process; -> Option B

4. Quick Check:

   Reset inside clock edge = correct synchronous reset syntax [OK]

Hint: Sensitivity list only clk; nest reset inside rising_edge(clk) for synchronous reset [OK]

Common Mistakes:

• Including reset in sensitivity list (makes it asynchronous)
• Checking reset outside clock edge
• Using elsif instead of nested if

3. Given the following VHDL process, what will be the value of q after the rising edge of clk if reset is '0' and d is '1'?

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. Undefined

B. '0'

C. '1'

D. Previous value of q

Solution

1. Step 1: Check reset condition

   Reset is '0', so the reset branch is skipped.

2. Step 2: Check clock edge and assignment

   On rising edge of clk, q is assigned the value of d, which is '1'.

3. Final Answer:

   '1' -> Option C

4. Quick Check:

   Reset '0' + rising clk = q = d = '1' [OK]

Hint: If reset is '0', q follows d on clock edge [OK]

Common Mistakes:

• Confusing reset active level
• Assuming q keeps old value without clock edge
• Ignoring sensitivity list effects

4. Identify the synthesis issue in the following VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      q <= d;
    end if;
end process;

medium

A. No issue; code is synthesizable as is

B. Syntax error due to missing sensitivity list signals

C. Unintended latch inferred because q is not assigned when enable = '0'

D. Process will not trigger on clock rising edge

Solution

1. Step 1: Analyze clocked process behavior

   In clocked processes, missing assignment in a branch implies hold previous value.

2. Step 2: Recognize standard template

   This is synthesizable as a flip-flop with enable; no latch inferred.

3. Final Answer:

   No issue; code is synthesizable as is -> Option A

4. Quick Check:

   Clocked process incomplete if = enabled FF hold [OK]

Hint: Incomplete assignments in clocked processes synthesize to enabled flip-flops [OK]

Common Mistakes:

• Confusing with combinational processes (which infer latches)
• Rewriting standard enabled FF template
• Mistaking intended hold for unintended latch

5. You want to design a synchronous counter with an active-high synchronous reset in VHDL. Which approach best avoids common synthesis pitfalls?

hard

A. Use a process with clock in sensitivity list; assign counter in all branches including reset and else

B. Use asynchronous reset only and assign counter only on clock rising edge

C. Assign counter only when reset is '0' and ignore other cases

D. Use combinational process without clock for counter increment

Solution

1. Step 1: Include only clock in sensitivity list

   For synchronous reset, only clock signal in process sensitivity list.

2. Step 2: Assign counter in all branches

   Assign counter to 0 on reset='1' and increment in else, all inside rising_edge(clk).

3. Final Answer:

   Use a process with clock in sensitivity list; assign counter in all branches including reset and else -> Option A

4. Quick Check:

   Synchronous reset + full assignments = safe synthesis [OK]

Hint: Always assign signals in all branches with clock in sensitivity list [OK]

Common Mistakes:

• Using asynchronous reset when synchronous is needed
• Missing assignments causing latches
• Using combinational logic for sequential counters