Variable vs signal inside process in VHDL - Visual Side-by-Side Comparison

Concept Flow - Variable vs signal inside process

Start Process

↓

Assign Variable

↓

Use Variable

↓

Assign Signal

↓

Use Signal

↓

End Process

↓

Signal Update Happens After Process Ends

Inside a VHDL process, variables update immediately and signals update only after the process finishes.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    var_x := var_x + 1;
    sig_y <= sig_y + 1;
  end if;
end process;

This process increments a variable and a signal on each clock rising edge.

Execution Table

Step	Action	Variable var_x	Signal sig_y	Notes
1	Start process, var_x=0, sig_y=0	0	0	Initial values
2	rising_edge(clk) true, var_x := var_x + 1	1	0	Variable updated immediately
3	sig_y <= sig_y + 1	1	0	Signal assignment scheduled, no immediate change
4	End process, signal updates	1	1	Signal sig_y updated after process ends
5	Next clock cycle start	1	1	Values ready for next cycle
6	rising_edge(clk) true, var_x := var_x + 1	2	1	Variable increments again immediately
7	sig_y <= sig_y + 1	2	1	Signal assignment scheduled again
8	End process, signal updates	2	2	Signal updated after process ends

💡 Process repeats on each clock rising edge; signals update after process finishes, variables update immediately.

Variable Tracker

Variable/Signal	Start	After 1	After 2	After 3	After 4
var_x	0	1	1	2	2
sig_y	0	0	1	1	2

Key Moments - 3 Insights

Why does var_x show the updated value immediately but sig_y does not?

Because variables update instantly inside the process (see step 2), but signals only update after the process ends (see step 4).

What happens to signal assignments inside the process before it ends?

Signal assignments are scheduled but do not change the signal's value until after the process finishes (see steps 3 and 4).

Can you use the updated signal value immediately after assigning it inside the same process?

No, the signal value remains the old one inside the process; updated signal values are visible only in the next process cycle.

Visual Quiz - 3 Questions

Look at the execution table, what is the value of var_x at step 3?

A 1

B 0

C 2

D Undefined

💡 Hint

Check the 'Variable var_x' column at step 3 in the execution_table.

At which step does sig_y actually update its value?

A Step 2

B Step 3

C Step 4

D Step 1

💡 Hint

Look at the 'Signal sig_y' column and note when it changes from 0 to 1.

If var_x was assigned using signal assignment (<=) instead of variable assignment (:=), what would happen at step 2?

A var_x would update immediately to 1

B var_x would cause an error

C var_x would remain 0 until process ends

D var_x would update after two cycles

💡 Hint

In VHDL, the assignment operator must match the target type: := for variables, <= for signals. Using <= on a variable causes a syntax error.

Concept Snapshot

Inside a VHDL process:
- Variables (:=) update immediately and can be used right away.
- Signals (<=) schedule updates that happen after the process ends.
- Use variables for temporary calculations inside process.
- Use signals to communicate outside the process.
- Signal updates visible only in next process cycle.

Full Transcript

This visual execution shows how variables and signals behave differently inside a VHDL process. Variables update immediately when assigned, so their new value is available right away inside the process. Signals, however, do not update immediately; their new value is scheduled and only takes effect after the process finishes. This means inside the same process, signal values remain old until the next cycle. The example process increments a variable and a signal on each clock rising edge. The execution table traces each step, showing variable var_x changing instantly and signal sig_y updating only after the process ends. Key moments clarify common confusions about immediate vs delayed updates. The quiz tests understanding of when values change and how assignments differ. Remember: variables are for quick internal use, signals for communicating outside the process.

Practice

1. In VHDL, inside a process, what is the main difference between a variable and a signal?

easy

A. Variables are visible outside the process; signals are local.

B. Signals update immediately; variables update after the process ends.

C. Variables update immediately; signals update after the process ends.

D. Signals use ':=' for assignment; variables use '<='.

Solution

1. Step 1: Understand variable update timing

   Variables inside a process update immediately when assigned using ':='.

2. Step 2: Understand signal update timing

   Signals update only after the process finishes, using '<=' assignment.

3. Final Answer:

   Variables update immediately; signals update after the process ends. -> Option C

4. Quick Check:

   Variable immediate update = A [OK]

Hint: Variables update instantly; signals wait until process ends [OK]

Common Mistakes:

• Confusing assignment operators ':=' and '<='
• Thinking signals update immediately inside process
• Assuming variables are visible outside the process

2. Which of the following is the correct way to assign a value to a variable inside a VHDL process?

easy

A. variable_var := '1';

B. signal_var <= '1';

C. variable_var <= '1';

D. signal_var := '1';

Solution

1. Step 1: Identify variable assignment syntax

   Variables inside a process use ':=' for assignment.

2. Step 2: Confirm correct option

   variable_var := '1'; uses ':=' with a variable, which is correct syntax.

3. Final Answer:

   variable_var := '1'; -> Option A

4. Quick Check:

   Variable assignment uses ':=' = B [OK]

Hint: Use ':=' for variables, '<=' for signals inside process [OK]

Common Mistakes:

• Using '<=' to assign variables
• Using ':=' to assign signals
• Mixing variable and signal names

3. Consider this VHDL process snippet:

process(clk)
begin
  if rising_edge(clk) then
    variable v : integer := 0;
    signal s : integer := 0;
    v := v + 1;
    s <= s + 1;
  end if;
end process;

What will be the value of v and s after the first clock rising edge?

medium

A. v = 0, s = 1

B. v = 1, s = 0

C. v = 1, s = 1

D. v = 0, s = 0

Solution

1. Step 1: Analyze variable update

   Variable v is initialized to 0 each clock, then incremented to 1 immediately.

2. Step 2: Analyze signal update

   Signal s is initialized to 0 each clock, but signal updates after process ends, so current value remains 0.

3. Final Answer:

   v = 1, s = 0 -> Option B

4. Quick Check:

   Variable immediate update, signal delayed update = C [OK]

Hint: Variables reset each run; signals update after process ends [OK]

Common Mistakes:

• Assuming signal updates immediately
• Forgetting variable re-initialization each clock
• Confusing variable and signal scopes

4. Identify the error in this VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    variable count : integer := 0;
    count <= count + 1;
  end if;
end process;

medium

A. Using '<=' to assign a variable inside process

B. Variable declared inside process

C. Missing signal declaration for count

D. No error, code is correct

Solution

1. Step 1: Check assignment operator for variable

   Variables must be assigned using ':=', not '<='.

2. Step 2: Confirm error

   Using '<=' on variable count causes syntax error.

3. Final Answer:

   Using '<=' to assign a variable inside process -> Option A

4. Quick Check:

   Variable assignment uses ':=' not '<=' = A [OK]

Hint: Variables use ':='; signals use '<=' inside process [OK]

Common Mistakes:

• Using '<=' for variables
• Thinking variables can't be declared inside process
• Confusing variable and signal declarations

5. You want to count the number of rising edges on a clock signal inside a process and use the count outside the process. Which is the correct approach?

hard

A. Use a variable to count inside the process and assign it to a signal after process ends.

B. Use a signal inside the process but assign it with ':='.

C. Use a variable only, since it updates immediately and is visible outside.

D. Use a signal to count inside the process with '<=' assignment.

Solution

1. Step 1: Understand visibility requirements

   Count must be visible outside process, so it must be a signal.

2. Step 2: Use correct assignment for signal

   Signals inside process are assigned with '<=' to update after process ends.

3. Final Answer:

   Use a signal to count inside the process with '<=' assignment. -> Option D

4. Quick Check:

   Signal visible outside, assigned with '<=' = D [OK]

Hint: Use signals for outside visibility; variables are local [OK]

Common Mistakes:

• Using variables expecting outside visibility
• Assigning signals with ':=' inside process
• Trying to assign variables outside process