Variable vs signal inside process in VHDL - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output difference between variable and signal inside a process

Consider the following VHDL process. What will be the output on out_signal after the process executes once?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    variable temp_var : integer := 0;
    temp_var := temp_var + 1;
    out_signal <= temp_var;
  end if;
end process;

A out_signal will be 0

B out_signal will be undefined

C out_signal will be 1

D out_signal will be 2

💡 Hint

Remember that variables inside a process update immediately, but signals update after the process ends.

The variable temp_var is initialized to 0 each time the process runs, then incremented to 1. The signal out_signal is assigned the value of temp_var, so it will be 1 after the process finishes.

❓ Predict Output

intermediate

Signal update timing inside a process

What will be the value of sig after the following process executes once on a rising clock edge?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    sig <= sig + 1;
    sig <= sig + 2;
  end if;
end process;

A sig will increase by 2

B sig will increase by 1

C sig will increase by 3

D sig will not change

💡 Hint

Signals assigned multiple times in the same process execution only take the last assignment value.

Both assignments to sig happen in the same process cycle. The last assignment sig <= sig + 2; overwrites the first. So sig increases by 2 only.

🔧 Debug

advanced

Why does this variable not retain its value between clock cycles?

Examine the process below. Why does count_var always reset to 0 on each clock cycle?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    variable count_var : integer := 0;
    count_var := count_var + 1;
    out_signal <= count_var;
  end if;
end process;

A Because signals cannot be assigned inside a process

B Because the variable is declared inside the process and reinitialized every time the process runs

C Because the variable is not declared as a signal

D Because the process is missing a reset condition

💡 Hint

Think about where the variable is declared and what happens each time the process runs.

The variable count_var is declared inside the process, so it is reinitialized to 0 every time the process executes. To retain its value, it should be declared outside the process or as a signal.

🧠 Conceptual

advanced

Difference in update timing between variable and signal inside a process

Which statement correctly describes the difference between variables and signals inside a VHDL process?

A Variables and signals update only after the process finishes

B Signals update immediately and variables update after the process finishes

C Both variables and signals update immediately inside a process

D Variables update immediately and their new value is visible within the same process execution; signals update after the process finishes

💡 Hint

Think about when you can see the new value of a variable versus a signal inside the same process.

Variables inside a process update immediately, so their new value can be used later in the same process execution. Signals update only after the process finishes, so their new value is not visible inside the same process run.

❓ Predict Output

expert

Final value of signal and variable after multiple assignments in a process

Given the following process, what are the final values of sig and var after one rising clock edge?

VHDL

process(clk)
begin
  if rising_edge(clk) then
    variable var : integer := 0;
    var := var + 1;
    var := var + 2;
    sig <= 0;
    sig <= var;
  end if;
end process;

A sig = 3, var = 3

B sig = 2, var = 3

C sig = 1, var = 3

D sig = 0, var = 3

💡 Hint

Remember variables update immediately and signals update after the process ends. Also, the last signal assignment wins.

The variable var starts at 0, then increments by 1 and 2, so var is 3. The signal sig is assigned 0, then immediately assigned var (3). The last assignment to sig takes effect, so sig becomes 3 after the process.

Practice

1. In VHDL, inside a process, what is the main difference between a variable and a signal?

easy

A. Variables are visible outside the process; signals are local.

B. Signals update immediately; variables update after the process ends.

C. Variables update immediately; signals update after the process ends.

D. Signals use ':=' for assignment; variables use '<='.

Solution

1. Step 1: Understand variable update timing

   Variables inside a process update immediately when assigned using ':='.

2. Step 2: Understand signal update timing

   Signals update only after the process finishes, using '<=' assignment.

3. Final Answer:

   Variables update immediately; signals update after the process ends. -> Option C

4. Quick Check:

   Variable immediate update = A [OK]

Hint: Variables update instantly; signals wait until process ends [OK]

Common Mistakes:

• Confusing assignment operators ':=' and '<='
• Thinking signals update immediately inside process
• Assuming variables are visible outside the process

2. Which of the following is the correct way to assign a value to a variable inside a VHDL process?

easy

A. variable_var := '1';

B. signal_var <= '1';

C. variable_var <= '1';

D. signal_var := '1';

Solution

1. Step 1: Identify variable assignment syntax

   Variables inside a process use ':=' for assignment.

2. Step 2: Confirm correct option

   variable_var := '1'; uses ':=' with a variable, which is correct syntax.

3. Final Answer:

   variable_var := '1'; -> Option A

4. Quick Check:

   Variable assignment uses ':=' = B [OK]

Hint: Use ':=' for variables, '<=' for signals inside process [OK]

Common Mistakes:

• Using '<=' to assign variables
• Using ':=' to assign signals
• Mixing variable and signal names

3. Consider this VHDL process snippet:

process(clk)
begin
  if rising_edge(clk) then
    variable v : integer := 0;
    signal s : integer := 0;
    v := v + 1;
    s <= s + 1;
  end if;
end process;

What will be the value of v and s after the first clock rising edge?

medium

A. v = 0, s = 1

B. v = 1, s = 0

C. v = 1, s = 1

D. v = 0, s = 0

Solution

1. Step 1: Analyze variable update

   Variable v is initialized to 0 each clock, then incremented to 1 immediately.

2. Step 2: Analyze signal update

   Signal s is initialized to 0 each clock, but signal updates after process ends, so current value remains 0.

3. Final Answer:

   v = 1, s = 0 -> Option B

4. Quick Check:

   Variable immediate update, signal delayed update = C [OK]

Hint: Variables reset each run; signals update after process ends [OK]

Common Mistakes:

• Assuming signal updates immediately
• Forgetting variable re-initialization each clock
• Confusing variable and signal scopes

4. Identify the error in this VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    variable count : integer := 0;
    count <= count + 1;
  end if;
end process;

medium

A. Using '<=' to assign a variable inside process

B. Variable declared inside process

C. Missing signal declaration for count

D. No error, code is correct

Solution

1. Step 1: Check assignment operator for variable

   Variables must be assigned using ':=', not '<='.

2. Step 2: Confirm error

   Using '<=' on variable count causes syntax error.

3. Final Answer:

   Using '<=' to assign a variable inside process -> Option A

4. Quick Check:

   Variable assignment uses ':=' not '<=' = A [OK]

Hint: Variables use ':='; signals use '<=' inside process [OK]

Common Mistakes:

• Using '<=' for variables
• Thinking variables can't be declared inside process
• Confusing variable and signal declarations

5. You want to count the number of rising edges on a clock signal inside a process and use the count outside the process. Which is the correct approach?

hard

A. Use a variable to count inside the process and assign it to a signal after process ends.

B. Use a signal inside the process but assign it with ':='.

C. Use a variable only, since it updates immediately and is visible outside.

D. Use a signal to count inside the process with '<=' assignment.

Solution

1. Step 1: Understand visibility requirements

   Count must be visible outside process, so it must be a signal.

2. Step 2: Use correct assignment for signal

   Signals inside process are assigned with '<=' to update after process ends.

3. Final Answer:

   Use a signal to count inside the process with '<=' assignment. -> Option D

4. Quick Check:

   Signal visible outside, assigned with '<=' = D [OK]

Hint: Use signals for outside visibility; variables are local [OK]

Common Mistakes:

• Using variables expecting outside visibility
• Assigning signals with ':=' inside process
• Trying to assign variables outside process