Register (multi-bit) design in VHDL - Step-by-Step Execution

Concept Flow - Register (multi-bit) design

Input Data (multi-bit)

↓

Clock Edge Detected?

No→Wait

Yes↓

Store Input in Register

↓

Output Register Value

The register waits for a clock edge, then stores the multi-bit input data and outputs the stored value.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    reg <= data_in;
  end if;
end process;

On each rising clock edge, the register stores the input data_in value.

Execution Table

Step	clk	rising_edge(clk)?	data_in	reg (before)	Action	reg (after)
1	0	No	1010	0000	No store	0000
2	1	Yes	1010	0000	Store data_in	1010
3	1	No	1100	1010	No store	1010
4	0	No	1100	1010	No store	1010
5	1	Yes	1100	1010	Store data_in	1100

💡 Simulation ends after 5 steps showing register updates on rising clock edges.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5
clk	0	1	1	1	0	1
data_in	1010	1010	1100	1100	1100	1100
reg	0000	0000	1010	1010	1010	1100

Key Moments - 2 Insights

Why does the register only update on certain steps?

The register updates only on rising edges of clk (when clk changes from 0 to 1), as shown in steps 2 and 5 in the execution_table.

Why doesn't the register change when data_in changes but clk does not rise?

The register stores data only on rising clock edges, so changes in data_in without a rising clk do not update reg, as seen in step 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of reg after step 2?

A 1010

B 0000

C 1100

D 1111

💡 Hint

Check the 'reg (after)' column at step 2 in the execution_table.

At which step does the register NOT update despite data_in changing?

A Step 2

B Step 3

C Step 5

D Step 1

💡 Hint

Look at step 3 in execution_table where data_in changes but reg stays the same.

If clk never rises, what will happen to reg?

A It updates with data_in every step

B It updates only on falling edge

C It never updates and stays at initial value

D It toggles randomly

💡 Hint

Refer to the 'rising_edge(clk)?' column in execution_table and how reg changes only on 'Yes'.

Concept Snapshot

VHDL multi-bit register stores input data on rising clock edge.
Syntax: process(clk) begin if rising_edge(clk) then reg <= data_in; end if; end process;
Register updates only on clock rising edge.
Data input changes alone do not update register.
Output is stored value until next clock edge.

Full Transcript

This visual trace shows a multi-bit register design in VHDL. The register waits for a rising clock edge to store the input data. The execution table tracks clock signal, input data, and register value step-by-step. The register updates only when the clock rises, ignoring input changes at other times. Variable tracking shows how clk, data_in, and reg change over time. Key moments clarify why register updates only on rising edges and not on input changes alone. The quiz tests understanding of register behavior at specific steps. The snapshot summarizes the register design and usage in VHDL.

Practice

1. What is the main purpose of a multi-bit register in VHDL?

easy

A. To generate clock signals

B. To perform arithmetic operations on data

C. To store multiple bits of data synchronized with a clock

D. To reset the entire circuit

Solution

1. Step 1: Understand the function of a register

   A register holds data bits and updates them based on a clock signal.

2. Step 2: Identify the main role of a multi-bit register

   It stores multiple bits of data synchronized by the clock, not arithmetic or clock generation.

3. Final Answer:

   To store multiple bits of data synchronized with a clock -> Option C

4. Quick Check:

   Multi-bit register = data storage [OK]

Hint: Registers hold data bits synced by clock signals [OK]

Common Mistakes:

• Confusing registers with arithmetic units
• Thinking registers generate clocks
• Assuming registers reset the whole circuit

2. Which of the following is the correct VHDL syntax to declare a 4-bit register signal named reg?

easy

A. signal reg : std_logic_vector(0 to 4);

B. signal reg : std_logic(4 downto 0);

C. signal reg : bit_vector(0 to 3);

D. signal reg : std_logic_vector(3 downto 0);

Solution

1. Step 1: Check the correct type for multi-bit signals

   std_logic_vector is used for multi-bit signals, not std_logic or bit_vector here.

2. Step 2: Verify the range for 4 bits

   4 bits means indices 3 downto 0 (4 bits total). signal reg : std_logic_vector(3 downto 0); matches this.

3. Final Answer:

   signal reg : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   4-bit vector = std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector with downto for bit ranges [OK]

Common Mistakes:

• Using std_logic instead of std_logic_vector for multiple bits
• Incorrect bit range size
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a 3-bit register with asynchronous reset:

process(clk, reset)
begin
  if reset = '1' then
    reg <= "000";
  elsif rising_edge(clk) then
    reg <= data_in;
  end if;
end process;

If reset is '0', clk rises, and data_in is "101", what will be the value of reg after the clock edge?

medium

A. "101"

B. Undefined

C. "111"

D. "000"

Solution

1. Step 1: Check reset condition

   Reset is '0', so register is not cleared to "000".

2. Step 2: Check clock edge and data assignment

   On rising edge of clk, reg takes the value of data_in, which is "101".

3. Final Answer:

   "101" -> Option A

4. Quick Check:

   Reset '0' + rising clk = reg = data_in [OK]

Hint: Reset '0' means register loads data on clock rise [OK]

Common Mistakes:

• Assuming reset clears register even when '0'
• Ignoring rising_edge(clk) condition
• Confusing asynchronous reset with synchronous

4. Identify the error in this VHDL code snippet for a 2-bit register with synchronous reset:

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      reg <= "00";
    else
      reg <= data_in;
    end if;
  end if;
end process;

medium

A. Reset signal should be in the sensitivity list

B. No error; code is correct

C. Reset should be asynchronous, not synchronous

D. Register signal reg is not declared

Solution

1. Step 1: Check sensitivity list for synchronous reset

   For synchronous reset inside clock edge, only clk is needed in sensitivity list.

2. Step 2: Verify if reset is asynchronous or synchronous

   Reset is synchronous here, so reset signal does not need to be in sensitivity list.

3. Step 3: Check for missing declarations

   Assuming reg is declared elsewhere, no error there.

4. Final Answer:

   No error; code is correct -> Option B

5. Quick Check:

   Synchronous reset inside clock process needs only clk [OK]

Hint: Synchronous reset needs only clk in sensitivity list [OK]

Common Mistakes:

• Adding reset to sensitivity list for synchronous reset
• Confusing synchronous and asynchronous reset requirements
• Assuming missing declarations without context

5. You want to design a 5-bit register with asynchronous active-high reset in VHDL. Which process structure correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) then
reg <= data_in;
end if;
end process;

B. process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
reg <= (others => '0');
else
reg <= data_in;
end if;
end if;
end process;

C. process(reset)
begin
if reset = '1' then
reg <= (others => '0');
end if;
end process;

D. process(clk)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) then
reg <= data_in;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset requirements

   Asynchronous reset requires reset signal in sensitivity list and immediate reset action.

2. Step 2: Check each option for reset and clock handling

   process(clk, reset) begin if reset = '1' then reg <= (others => '0'); elsif rising_edge(clk) then reg <= data_in; end if; end process; includes reset and clk in sensitivity list and resets immediately if reset='1'.

3. Step 3: Verify other options

   process(clk) begin if rising_edge(clk) then if reset = '1' then reg <= (others => '0'); else reg <= data_in; end if; end if; end process; is synchronous reset (reset inside clock edge). process(reset) begin if reset = '1' then reg <= (others => '0'); end if; end process; lacks clock. process(clk) begin if reset = '1' then reg <= (others => '0'); elsif rising_edge(clk) then reg <= data_in; end if; end process; misses reset in sensitivity list.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then reg <= (others => '0'); elsif rising_edge(clk) then reg <= data_in; end if; end process; -> Option A

5. Quick Check:

   Async reset = reset in sensitivity list + immediate reset [OK]

Hint: Async reset needs reset in sensitivity list and immediate action [OK]

Common Mistakes:

• Placing asynchronous reset inside clock edge
• Omitting reset from sensitivity list
• Using synchronous reset when async is required