Register (multi-bit) design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output of this 4-bit register after one clock cycle?

Consider this VHDL code for a 4-bit register with synchronous reset. What will be the value of q after the rising edge of the clock if reset = '0' and d = "1010"?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg4 is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           d : in STD_LOGIC_VECTOR (3 downto 0);
           q : out STD_LOGIC_VECTOR (3 downto 0));
end reg4;

architecture Behavioral of reg4 is
    signal reg_q : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_q <= (others => '0');
            else
                reg_q <= d;
            end if;
        end if;
    end process;
    q <= reg_q;
end Behavioral;

A "0000"

B "1010"

C "1111"

D "0101"

💡 Hint

Remember that the register updates q only on the rising edge of clk and reset is synchronous.

Since reset is '0', the register loads the input d on the rising edge of clk. Therefore, q becomes "1010".

❓ Predict Output

intermediate

What is the value of q after reset is asserted?

Given this 8-bit register with asynchronous reset, what will be the value of q immediately after reset = '1' is asserted?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg8_async is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           d : in STD_LOGIC_VECTOR (7 downto 0);
           q : out STD_LOGIC_VECTOR (7 downto 0));
end reg8_async;

architecture Behavioral of reg8_async is
    signal reg_q : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            reg_q <= (others => '0');
        elsif rising_edge(clk) then
            reg_q <= d;
        end if;
    end process;
    q <= reg_q;
end Behavioral;

A "00000000"

B Previous value of q

C Undefined

D "11111111"

💡 Hint

Asynchronous reset sets the register output immediately when asserted.

Because reset is asynchronous and active high, when reset = '1', q is immediately set to all zeros regardless of the clock.

🔧 Debug

advanced

Identify the error in this 3-bit register design

What is the error in this VHDL code for a 3-bit register with synchronous reset?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg3 is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           d : in STD_LOGIC_VECTOR (2 downto 0);
           q : out STD_LOGIC_VECTOR (2 downto 0));
end reg3;

architecture Behavioral of reg3 is
    signal reg_q : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_q <= (others => '0');
            else
                reg_q <= d;
            end if;
        end if;
    end process;
    q <= reg_q;
end Behavioral;

A Signal reg_q should be declared as std_logic, not vector

B Missing sensitivity to reset in process sensitivity list

C Output q should be a signal, not port

D Reset check should be inside rising_edge(clk) condition

💡 Hint

Think about synchronous reset behavior and where the reset condition should be checked.

For synchronous reset, the reset condition must be checked inside the if rising_edge(clk) block. Checking reset outside causes unintended asynchronous behavior.

📝 Syntax

advanced

Which option causes a syntax error in this multi-bit register code?

Which of the following VHDL code snippets for a 2-bit register will cause a syntax error?

A

;ssecorp dne
;fi dne  
;d =< q    
neht )klc(egde_gnisir fi  
nigeb
)klc(ssecorp

B

process(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

C

process(clk)
begin
  if rising_edge(clk) then
    q <= d
  end if;
end process;

D

rocess(clk)
begin
  if rising_edge(clk) then
    q <= d;
  end if;
end process;

💡 Hint

Check for missing semicolons in the code.

Option C is missing a semicolon after q <= d, causing a syntax error.

🚀 Application

expert

How many bits are stored in this register design?

Given this VHDL entity for a register, how many bits does it store?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg_custom is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           d : in STD_LOGIC_VECTOR (15 downto 4);
           q : out STD_LOGIC_VECTOR (15 downto 4));
end reg_custom;

architecture Behavioral of reg_custom is
    signal reg_q : STD_LOGIC_VECTOR(15 downto 4) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_q <= (others => '0');
            else
                reg_q <= d;
            end if;
        end if;
    end process;
    q <= reg_q;
end Behavioral;

A 12 bits

B 16 bits

C 11 bits

D 15 bits

💡 Hint

Count the bits from index 15 down to 4.

The vector ranges from 15 down to 4, which is 15 - 4 + 1 = 12 bits.

Practice

1. What is the main purpose of a multi-bit register in VHDL?

easy

A. To generate clock signals

B. To perform arithmetic operations on data

C. To store multiple bits of data synchronized with a clock

D. To reset the entire circuit

Solution

1. Step 1: Understand the function of a register

   A register holds data bits and updates them based on a clock signal.

2. Step 2: Identify the main role of a multi-bit register

   It stores multiple bits of data synchronized by the clock, not arithmetic or clock generation.

3. Final Answer:

   To store multiple bits of data synchronized with a clock -> Option C

4. Quick Check:

   Multi-bit register = data storage [OK]

Hint: Registers hold data bits synced by clock signals [OK]

Common Mistakes:

• Confusing registers with arithmetic units
• Thinking registers generate clocks
• Assuming registers reset the whole circuit

2. Which of the following is the correct VHDL syntax to declare a 4-bit register signal named reg?

easy

A. signal reg : std_logic_vector(0 to 4);

B. signal reg : std_logic(4 downto 0);

C. signal reg : bit_vector(0 to 3);

D. signal reg : std_logic_vector(3 downto 0);

Solution

1. Step 1: Check the correct type for multi-bit signals

   std_logic_vector is used for multi-bit signals, not std_logic or bit_vector here.

2. Step 2: Verify the range for 4 bits

   4 bits means indices 3 downto 0 (4 bits total). signal reg : std_logic_vector(3 downto 0); matches this.

3. Final Answer:

   signal reg : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   4-bit vector = std_logic_vector(3 downto 0) [OK]

Hint: Use std_logic_vector with downto for bit ranges [OK]

Common Mistakes:

• Using std_logic instead of std_logic_vector for multiple bits
• Incorrect bit range size
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a 3-bit register with asynchronous reset:

process(clk, reset)
begin
  if reset = '1' then
    reg <= "000";
  elsif rising_edge(clk) then
    reg <= data_in;
  end if;
end process;

If reset is '0', clk rises, and data_in is "101", what will be the value of reg after the clock edge?

medium

A. "101"

B. Undefined

C. "111"

D. "000"

Solution

1. Step 1: Check reset condition

   Reset is '0', so register is not cleared to "000".

2. Step 2: Check clock edge and data assignment

   On rising edge of clk, reg takes the value of data_in, which is "101".

3. Final Answer:

   "101" -> Option A

4. Quick Check:

   Reset '0' + rising clk = reg = data_in [OK]

Hint: Reset '0' means register loads data on clock rise [OK]

Common Mistakes:

• Assuming reset clears register even when '0'
• Ignoring rising_edge(clk) condition
• Confusing asynchronous reset with synchronous

4. Identify the error in this VHDL code snippet for a 2-bit register with synchronous reset:

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      reg <= "00";
    else
      reg <= data_in;
    end if;
  end if;
end process;

medium

A. Reset signal should be in the sensitivity list

B. No error; code is correct

C. Reset should be asynchronous, not synchronous

D. Register signal reg is not declared

Solution

1. Step 1: Check sensitivity list for synchronous reset

   For synchronous reset inside clock edge, only clk is needed in sensitivity list.

2. Step 2: Verify if reset is asynchronous or synchronous

   Reset is synchronous here, so reset signal does not need to be in sensitivity list.

3. Step 3: Check for missing declarations

   Assuming reg is declared elsewhere, no error there.

4. Final Answer:

   No error; code is correct -> Option B

5. Quick Check:

   Synchronous reset inside clock process needs only clk [OK]

Hint: Synchronous reset needs only clk in sensitivity list [OK]

Common Mistakes:

• Adding reset to sensitivity list for synchronous reset
• Confusing synchronous and asynchronous reset requirements
• Assuming missing declarations without context

5. You want to design a 5-bit register with asynchronous active-high reset in VHDL. Which process structure correctly implements this behavior?

hard

A. process(clk, reset)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) then
reg <= data_in;
end if;
end process;

B. process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
reg <= (others => '0');
else
reg <= data_in;
end if;
end if;
end process;

C. process(reset)
begin
if reset = '1' then
reg <= (others => '0');
end if;
end process;

D. process(clk)
begin
if reset = '1' then
reg <= (others => '0');
elsif rising_edge(clk) then
reg <= data_in;
end if;
end process;

Solution

1. Step 1: Identify asynchronous reset requirements

   Asynchronous reset requires reset signal in sensitivity list and immediate reset action.

2. Step 2: Check each option for reset and clock handling

   process(clk, reset) begin if reset = '1' then reg <= (others => '0'); elsif rising_edge(clk) then reg <= data_in; end if; end process; includes reset and clk in sensitivity list and resets immediately if reset='1'.

3. Step 3: Verify other options

   process(clk) begin if rising_edge(clk) then if reset = '1' then reg <= (others => '0'); else reg <= data_in; end if; end if; end process; is synchronous reset (reset inside clock edge). process(reset) begin if reset = '1' then reg <= (others => '0'); end if; end process; lacks clock. process(clk) begin if reset = '1' then reg <= (others => '0'); elsif rising_edge(clk) then reg <= data_in; end if; end process; misses reset in sensitivity list.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then reg <= (others => '0'); elsif rising_edge(clk) then reg <= data_in; end if; end process; -> Option A

5. Quick Check:

   Async reset = reset in sensitivity list + immediate reset [OK]

Hint: Async reset needs reset in sensitivity list and immediate action [OK]

Common Mistakes:

• Placing asynchronous reset inside clock edge
• Omitting reset from sensitivity list
• Using synchronous reset when async is required