Modulo-N counter in VHDL - Mini Project: Build & Apply

Modulo-N counter

📖 Scenario: You are designing a simple digital counter that counts from 0 up to a number N-1 and then wraps back to 0. This is called a modulo-N counter. It is useful in many electronics projects like timers, clocks, and event counters.

🎯 Goal: Build a modulo-N counter in VHDL that counts from 0 to N-1 and then resets to 0 automatically.

📋 What You'll Learn

Create a signal to hold the current count

Create a constant N for the modulo value

Write a process that increments the count on each clock rising edge

Reset the count to 0 when it reaches N

Print or output the current count value

💡 Why This Matters

🌍 Real World

Modulo-N counters are used in digital clocks, timers, frequency dividers, and event counters where counting cycles or events within a fixed range is needed.

💼 Career

Understanding counters and VHDL processes is essential for FPGA and ASIC design engineers working on digital hardware systems.

1

Create the counter signal

Create a signal called count of type integer initialized to 0 inside the architecture.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity ModuloCounter is
    port(
        clk : in std_logic;
        reset : in std_logic;
        count_out : out integer
    );
end ModuloCounter;

architecture Behavioral of ModuloCounter is
    signal count : integer := 0;  -- Your code here
begin

end Behavioral;

Hint

Signals hold values that can change over time inside the architecture. Initialize count to 0.

2

Add the modulo constant N

Inside the architecture, create a constant called N of type integer and set it to 5.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity ModuloCounter is
    port(
        clk : in std_logic;
        reset : in std_logic;
        count_out : out integer
    );
end ModuloCounter;

architecture Behavioral of ModuloCounter is
    constant N : integer := 5;  -- Your code here
    signal count : integer := 0;
begin

end Behavioral;

Hint

Constants hold fixed values. Set N to 5 for counting from 0 to 4.

3

Write the counting process

Write a process sensitive to clk and reset. Inside, on rising edge of clk, if reset is '1' then set count to 0. Otherwise, if count is less than N - 1, increment count by 1. Else, reset count to 0.

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity ModuloCounter is
    port(
        clk : in std_logic;
        reset : in std_logic;
        count_out : out integer
    );
end ModuloCounter;

architecture Behavioral of ModuloCounter is
    constant N : integer := 5;
    signal count : integer := 0;
begin
    process(clk, reset)
    begin
        -- Your code here
    end process;
end Behavioral;

Hint

Use rising_edge(clk) to detect clock ticks. Reset count on reset = '1'. Increment count until it reaches N - 1, then reset to 0.

4

Output the count value

Assign the signal count to the output port count_out so the current count value is available outside the module. Then, add a simple print statement inside the process to display the count value on each clock rising edge when not resetting.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity ModuloCounter is
    port(
        clk : in std_logic;
        reset : in std_logic;
        count_out : out integer
    );
end ModuloCounter;

architecture Behavioral of ModuloCounter is
    constant N : integer := 5;
    signal count : integer := 0;
begin
    count_out <= count;  -- Your code here
    process(clk, reset)
    begin
        if reset = '1' then
            count <= 0;
        elsif rising_edge(clk) then
            if count < N - 1 then
                count <= count + 1;
            else
                count <= 0;
            end if;
            -- Add print statement here
        end if;
    end process;
end Behavioral;

Hint

Assign count to count_out so external modules can see it. Use report with integer'image(count) to print the count value.

Practice

1. What does a Modulo-N counter do in VHDL?

easy

A. Counts from 0 up to N-1 and then restarts at 0

B. Counts from N down to 0 and stops

C. Counts only even numbers up to N

D. Counts from 1 to N without restarting

Solution

1. Step 1: Understand the counting range

   A Modulo-N counter counts starting at 0 and goes up to N-1.

2. Step 2: Recognize the restart behavior

   After reaching N-1, it restarts counting from 0 again.

3. Final Answer:

   Counts from 0 up to N-1 and then restarts at 0 -> Option A

4. Quick Check:

   Modulo-N counter = Counts 0 to N-1 then resets [OK]

Hint: Remember: Modulo means count resets after N-1 [OK]

Common Mistakes:

• Thinking it counts down instead of up
• Assuming it counts from 1 instead of 0
• Believing it stops after reaching N-1

2. Which of the following is the correct VHDL syntax to declare a signal for a 4-bit Modulo-16 counter?

easy

A. signal count : std_logic_vector(15 downto 0);

B. signal count : integer range 1 to 16;

C. signal count : integer range 0 to 15;

D. signal count : std_logic_vector(4 downto 0);

Solution

1. Step 1: Identify the correct data type and range

   For a Modulo-16 counter, integer range 0 to 15 covers all counts from 0 to 15.

2. Step 2: Check signal declaration syntax

   "signal count : integer range 0 to 15;" is valid VHDL syntax for this purpose.

3. Final Answer:

   signal count : integer range 0 to 15; -> Option C

4. Quick Check:

   Integer 0 to 15 fits 4-bit Modulo-16 counter [OK]

Hint: Use integer range 0 to N-1 for Modulo-N counters [OK]

Common Mistakes:

• Using std_logic_vector with wrong bit width
• Setting range from 1 to N instead of 0 to N-1
• Confusing bit width with integer range

3. Given the following VHDL process for a Modulo-4 counter, what is the value of count after 5 rising clock edges (assuming reset is inactive)?

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if count = 3 then
      count <= 0;
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. 1

B. 2

C. 0

D. 3

Solution

1. Step 1: Trace count values on each clock edge

   Starting at 0, count increments each clock: 0->1->2->3->0->1 after 5 edges.

2. Step 2: Identify count after 5 edges

   After 5 rising edges (1st:1, 2nd:2, 3rd:3, 4th:0, 5th:1), count is 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   Modulo-4 resets at 3, so after 5 edges count = 1 [OK]

Hint: Count resets after reaching N-1, track each clock edge [OK]

Common Mistakes:

• Counting from 1 instead of 0
• Forgetting the reset at count = 3
• Miscounting the number of clock edges

4. Identify the error in this VHDL code snippet for a Modulo-8 counter:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if count = 8 then
      count <= 0;
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. The reset condition should check for '0' instead of '1'

B. The count signal is not declared as std_logic_vector

C. The process is missing a sensitivity list

D. The count comparison should be 'count = 7' instead of 'count = 8'

Solution

1. Step 1: Check the counting limit for Modulo-8

   Modulo-8 counts from 0 to 7, so the reset should happen when count = 7.

2. Step 2: Identify the incorrect comparison

   The code compares count = 8, which is outside the valid range, causing incorrect behavior.

3. Final Answer:

   The count comparison should be 'count = 7' instead of 'count = 8' -> Option D

4. Quick Check:

   Modulo-8 max count = 7, not 8 [OK]

Hint: Check if count comparison matches N-1 for Modulo-N [OK]

Common Mistakes:

• Using count = N instead of count = N-1
• Confusing reset signal polarity
• Ignoring sensitivity list correctness

5. You want to design a Modulo-10 counter in VHDL that counts from 0 to 9 and then resets. Which of the following code snippets correctly implements this behavior inside a clocked process?

hard

A. if reset = '0' then
count <= 0;
elsif rising_edge(clk) then
if count = 10 then
count <= 0;
else
count <= count + 1;
end if;

B. if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
if count = 9 then
count <= 0;
else
count <= count + 1;
end if;

C. if reset = '1' then
count <= 1;
elsif rising_edge(clk) then
if count = 10 then
count <= 1;
else
count <= count + 1;
end if;

D. if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
if count = 10 then
count <= 1;
else
count <= count + 1;
end if;

Solution

1. Step 1: Check reset condition and initial count

   Reset should set count to 0, which is done correctly only in if reset = '1' then count <= 0; elsif rising_edge(clk) then if count = 9 then count <= 0; else count <= count + 1; end if;.

2. Step 2: Verify counting and reset limit

   Counting should reset when count = 9 (for Modulo-10), and then count restarts at 0, correctly shown in if reset = '1' then count <= 0; elsif rising_edge(clk) then if count = 9 then count <= 0; else count <= count + 1; end if;.

3. Final Answer:

   resets count at 9 and initializes at 0 -> Option B

4. Quick Check:

   Modulo-10 counts 0 to 9, reset at 9 [OK]

Hint: Reset at N-1 and start count at 0 for Modulo-N [OK]

Common Mistakes:

• Resetting count to 1 instead of 0
• Using count = N instead of count = N-1 for reset
• Incorrect reset signal polarity