Modulo-N counter in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple Modulo-4 counter process

Consider the following VHDL process for a Modulo-4 counter. What is the value of count after 5 rising clock edges?

VHDL

process(clk)
  variable count : integer range 0 to 3 := 0;
begin
  if rising_edge(clk) then
    if count = 3 then
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

A 3

B 0

C 2

D 1

💡 Hint

Count cycles from 0 to 3 and resets after 3.

The counter starts at 0. After 1st clock edge: 1, 2nd: 2, 3rd: 3, 4th: 0 (reset), 5th: 1, so after 5 edges count is 1. But since variable count is updated inside process, the value after 5 edges is 1. The correct answer is 1.

🧠 Conceptual

intermediate

Understanding Modulo-N counter range

If you want to design a Modulo-10 counter in VHDL using an integer variable, what should be the correct range declaration for the counter variable?

A integer range 0 to 9

B integer range 1 to 10

C integer range 0 to 10

D integer range 1 to 9

💡 Hint

Modulo-10 means counting 10 states starting from 0.

A Modulo-10 counter counts from 0 up to 9, then resets to 0. So the range should be 0 to 9.

🔧 Debug

advanced

Identify the error in this Modulo-5 counter code

What error will this VHDL code cause when synthesizing a Modulo-5 counter? process(clk) variable count : integer range 0 to 4 := 0; begin if rising_edge(clk) then if count = 5 then count := 0; else count := count + 1; end if; end if; end process;

A Range check error because count can never be 5

B Syntax error due to missing semicolon

C No error, code synthesizes correctly

D Runtime error due to variable not initialized

💡 Hint

Check the variable range and the condition in the if statement.

The variable 'count' is declared with range 0 to 4, so it can never be 5. The condition 'if count = 5' is unreachable and causes a range check error.

📝 Syntax

advanced

Syntax error in Modulo-N counter process

Which option contains the correct syntax for a Modulo-3 counter process in VHDL?

VHDL

process(clk)
  variable count : integer range 0 to 2 := 0;
begin
  if rising_edge(clk) then
    if count = 2 then
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

A

process(clk)
  variable count : integer range 0 to 2 := 0;
begin
  if rising_edge(clk) then
    if count = 2 then
      count := 0
    else
      count := count + 1;
    end if;
  end if;
end process;

B

process(clk)
  variable count : integer range 0 to 2 := 0;
begin
  if rising_edge(clk) then
    if count = 2 then
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

C

process(clk)
  variable count : integer range 0 to 2 := 0;
begin
  if rising_edge(clk) then
    if count = 2 then
      count = 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

D

process(clk)
  variable count : integer range 0 to 2 := 0
begin
  if rising_edge(clk) then
    if count = 2 then
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

💡 Hint

Check for missing semicolons and correct assignment operator.

Option B has correct syntax with semicolons and uses ':=' for assignment. Option B misses semicolon after variable declaration. Option B uses '=' instead of ':=' for assignment. Option B misses semicolon after 'count := 0'.

🚀 Application

expert

Design behavior of a Modulo-6 counter with asynchronous reset

Given this VHDL code snippet for a Modulo-6 counter with asynchronous reset, what will be the value of count after the following sequence: reset asserted (count resets), then 7 rising clock edges?

process(clk, reset)
  variable count : integer range 0 to 5 := 0;
begin
  if reset = '1' then
    count := 0;
  elsif rising_edge(clk) then
    if count = 5 then
      count := 0;
    else
      count := count + 1;
    end if;
  end if;
end process;

A 5

B 2

C 1

D 0

💡 Hint

Count starts at 0 after reset, then increments modulo 6.

After reset, count is 0. Then 7 clock edges increment count: 0->1->2->3->4->5->0->1. After 7 edges, count is 1. But since variable updates inside process, after 7 edges count is 1. The correct answer is 1.

Practice

1. What does a Modulo-N counter do in VHDL?

easy

A. Counts from 0 up to N-1 and then restarts at 0

B. Counts from N down to 0 and stops

C. Counts only even numbers up to N

D. Counts from 1 to N without restarting

Solution

1. Step 1: Understand the counting range

   A Modulo-N counter counts starting at 0 and goes up to N-1.

2. Step 2: Recognize the restart behavior

   After reaching N-1, it restarts counting from 0 again.

3. Final Answer:

   Counts from 0 up to N-1 and then restarts at 0 -> Option A

4. Quick Check:

   Modulo-N counter = Counts 0 to N-1 then resets [OK]

Hint: Remember: Modulo means count resets after N-1 [OK]

Common Mistakes:

• Thinking it counts down instead of up
• Assuming it counts from 1 instead of 0
• Believing it stops after reaching N-1

2. Which of the following is the correct VHDL syntax to declare a signal for a 4-bit Modulo-16 counter?

easy

A. signal count : std_logic_vector(15 downto 0);

B. signal count : integer range 1 to 16;

C. signal count : integer range 0 to 15;

D. signal count : std_logic_vector(4 downto 0);

Solution

1. Step 1: Identify the correct data type and range

   For a Modulo-16 counter, integer range 0 to 15 covers all counts from 0 to 15.

2. Step 2: Check signal declaration syntax

   "signal count : integer range 0 to 15;" is valid VHDL syntax for this purpose.

3. Final Answer:

   signal count : integer range 0 to 15; -> Option C

4. Quick Check:

   Integer 0 to 15 fits 4-bit Modulo-16 counter [OK]

Hint: Use integer range 0 to N-1 for Modulo-N counters [OK]

Common Mistakes:

• Using std_logic_vector with wrong bit width
• Setting range from 1 to N instead of 0 to N-1
• Confusing bit width with integer range

3. Given the following VHDL process for a Modulo-4 counter, what is the value of count after 5 rising clock edges (assuming reset is inactive)?

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if count = 3 then
      count <= 0;
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. 1

B. 2

C. 0

D. 3

Solution

1. Step 1: Trace count values on each clock edge

   Starting at 0, count increments each clock: 0->1->2->3->0->1 after 5 edges.

2. Step 2: Identify count after 5 edges

   After 5 rising edges (1st:1, 2nd:2, 3rd:3, 4th:0, 5th:1), count is 1.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   Modulo-4 resets at 3, so after 5 edges count = 1 [OK]

Hint: Count resets after reaching N-1, track each clock edge [OK]

Common Mistakes:

• Counting from 1 instead of 0
• Forgetting the reset at count = 3
• Miscounting the number of clock edges

4. Identify the error in this VHDL code snippet for a Modulo-8 counter:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if count = 8 then
      count <= 0;
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. The reset condition should check for '0' instead of '1'

B. The count signal is not declared as std_logic_vector

C. The process is missing a sensitivity list

D. The count comparison should be 'count = 7' instead of 'count = 8'

Solution

1. Step 1: Check the counting limit for Modulo-8

   Modulo-8 counts from 0 to 7, so the reset should happen when count = 7.

2. Step 2: Identify the incorrect comparison

   The code compares count = 8, which is outside the valid range, causing incorrect behavior.

3. Final Answer:

   The count comparison should be 'count = 7' instead of 'count = 8' -> Option D

4. Quick Check:

   Modulo-8 max count = 7, not 8 [OK]

Hint: Check if count comparison matches N-1 for Modulo-N [OK]

Common Mistakes:

• Using count = N instead of count = N-1
• Confusing reset signal polarity
• Ignoring sensitivity list correctness

5. You want to design a Modulo-10 counter in VHDL that counts from 0 to 9 and then resets. Which of the following code snippets correctly implements this behavior inside a clocked process?

hard

A. if reset = '0' then
count <= 0;
elsif rising_edge(clk) then
if count = 10 then
count <= 0;
else
count <= count + 1;
end if;

B. if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
if count = 9 then
count <= 0;
else
count <= count + 1;
end if;

C. if reset = '1' then
count <= 1;
elsif rising_edge(clk) then
if count = 10 then
count <= 1;
else
count <= count + 1;
end if;

D. if reset = '1' then
count <= 0;
elsif rising_edge(clk) then
if count = 10 then
count <= 1;
else
count <= count + 1;
end if;

Solution

1. Step 1: Check reset condition and initial count

   Reset should set count to 0, which is done correctly only in if reset = '1' then count <= 0; elsif rising_edge(clk) then if count = 9 then count <= 0; else count <= count + 1; end if;.

2. Step 2: Verify counting and reset limit

   Counting should reset when count = 9 (for Modulo-10), and then count restarts at 0, correctly shown in if reset = '1' then count <= 0; elsif rising_edge(clk) then if count = 9 then count <= 0; else count <= count + 1; end if;.

3. Final Answer:

   resets count at 9 and initializes at 0 -> Option B

4. Quick Check:

   Modulo-10 counts 0 to 9, reset at 9 [OK]

Hint: Reset at N-1 and start count at 0 for Modulo-N [OK]

Common Mistakes:

• Resetting count to 1 instead of 0
• Using count = N instead of count = N-1 for reset
• Incorrect reset signal polarity