If-then-else in process in VHDL - Step-by-Step Execution

Concept Flow - If-then-else in process

Start Process

↓

Evaluate condition

↓

Execute

↓

Then

↓

End Process

The process starts, checks the condition, executes the 'then' block if true, otherwise executes the 'else' block, then ends.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if a = '1' then
      y <= '1';
    else
      y <= '0';
    end if;
  end if;
end process;

This process checks for a clock rising edge, then sets output y to '1' if input a is '1', else sets y to '0'.

Execution Table

Step	Condition (rising_edge(clk))	Condition (a = '1')	Branch Taken	Signal y Assignment
1	False	N/A	No action	y unchanged
2	True	True	Then branch	y <= '1'
3	True	False	Else branch	y <= '0'

💡 Process waits for rising_edge(clk) to be True to execute if-then-else.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3
clk	0	0	1 (rising edge)	1
a	'0'	'0'	'1'	'0'
y	'0'	'0'	'1'	'0'

Key Moments - 2 Insights

Why does the process not assign y when rising_edge(clk) is False?

Because the outer if condition (rising_edge(clk)) is False, the inner if-then-else is skipped, so y remains unchanged as shown in Step 1 of the execution_table.

What happens if a is neither '1' nor '0'?

In VHDL, 'a' is a std_logic and can have multiple values, but the condition checks specifically for '1'. If 'a' is not '1', the else branch runs, assigning y <= '0' as shown in Step 3.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of y after Step 2?

A '1'

B '0'

C Unchanged

D Undefined

💡 Hint

Check the 'Signal y Assignment' column at Step 2 in the execution_table.

At which step does the process skip assigning y because the clock edge condition is False?

A Step 3

B Step 2

C Step 1

D Never

💡 Hint

Look at the 'Condition (rising_edge(clk))' column in the execution_table.

If input a is '0' and rising_edge(clk) is True, what branch is taken?

A Then branch

B Else branch

C No branch

D Both branches

💡 Hint

Refer to Step 3 in the execution_table where a = '0' and the else branch is taken.

Concept Snapshot

VHDL if-then-else in process:
process triggered by clock or signals
if condition then
  -- then statements
else
  -- else statements
end if;
Executes 'then' block if condition true, else 'else' block.

Full Transcript

This VHDL process waits for a rising edge on the clock signal. When the clock rises, it checks if input 'a' equals '1'. If yes, it assigns '1' to output 'y'. Otherwise, it assigns '0' to 'y'. If the clock does not rise, the process does nothing and 'y' remains unchanged. This shows how if-then-else controls signal assignments inside a process based on conditions.

Practice

1. What is the main purpose of using if-then-else inside a VHDL process?

easy

A. To specify the clock frequency

B. To declare new signals

C. To choose different actions based on conditions

D. To define the entity interface

Solution

1. Step 1: Understand the role of if-then-else in VHDL process

   The if-then-else statement allows the process to select different actions depending on the condition evaluated.

2. Step 2: Compare other options

   Declaring signals, defining entity interface, and specifying clock frequency are unrelated to if-then-else usage inside a process.

3. Final Answer:

   To choose different actions based on conditions -> Option C

4. Quick Check:

   If-then-else controls actions by conditions [OK]

Hint: If-then-else picks actions based on conditions [OK]

Common Mistakes:

• Confusing if-then-else with signal declaration
• Thinking if-then-else defines entity ports
• Assuming it sets clock frequency

2. Which of the following is the correct syntax for an if-then-else statement inside a VHDL process?

easy

A. if (condition) { signal = '1'; } else { signal = '0'; }

B. if condition then signal <= '1'; else signal <= '0'; end if;

C. if condition: signal = '1' else signal = '0'

D. if condition then signal = 1 else signal = 0 end if

Solution

1. Step 1: Review VHDL if-then-else syntax

   VHDL uses 'if condition then ... else ... end if;' with signal assignment using '<=' and single quotes for bits.

2. Step 2: Check each option

   if condition then signal <= '1'; else signal <= '0'; end if; matches correct syntax. Options B and C use other languages' syntax. if condition then signal = 1 else signal = 0 end if misses semicolons and uses '=' instead of '<='.

3. Final Answer:

   if condition then signal <= '1'; else signal <= '0'; end if; -> Option B

4. Quick Check:

   VHDL if-then-else uses 'then', '<=', and 'end if;' [OK]

Hint: VHDL uses 'then', '<=', and ends with 'end if;' [OK]

Common Mistakes:

• Using curly braces or parentheses like other languages
• Using '=' instead of '<=' for signal assignment
• Omitting semicolons or 'end if;'

3. Consider the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    if input = '1' then
      output <= '0';
    else
      output <= '1';
    end if;
  end if;
end process;

What will be the value of output after a rising clock edge if input is '1'?

medium

A. '0'

B. Undefined

C. '1'

D. 'Z'

Solution

1. Step 1: Analyze the process on rising clock edge

   When clk rises, the process checks if input = '1'. If true, output is assigned '0'.

2. Step 2: Apply input value '1'

   Since input = '1', output <= '0' is executed.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Input '1' sets output to '0' [OK]

Hint: Check condition inside rising_edge block carefully [OK]

Common Mistakes:

• Ignoring the nested if condition
• Confusing output with input value
• Assuming output stays unchanged

4. Identify the error in this VHDL process:

process(clk)
begin
  if clk'event and clk = '1' then
    if input = '1' then
      output <= '1'
    else
      output <= '0';
    end if;
  end if;
end process;

medium

A. Missing semicolon after output <= '1'

B. Wrong sensitivity list

C. Incorrect use of clk'event

D. Missing end if; for outer if

Solution

1. Step 1: Check each statement for syntax errors

   Inside the inner if, the line output <= '1' lacks a semicolon at the end.

2. Step 2: Verify other parts

   Sensitivity list includes clk, which is correct. clk'event and clk = '1' is valid for rising edge detection. The outer if has matching end if;.

3. Final Answer:

   Missing semicolon after output <= '1' -> Option A

4. Quick Check:

   Every statement must end with semicolon [OK]

Hint: Check semicolons after every assignment line [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing clk'event with rising_edge(clk)
• Missing end if for if statements

5. You want to design a VHDL process that sets output to '1' if input1 is '1' and input2 is '0', otherwise sets output to '0'. Which is the correct if-then-else structure inside a clocked process?

hard

A. if rising_edge(clk) then
if input1 = '1' and input2 = '0' then
output <= '1'
else
output <= '0';
end if;
end if;

B. if rising_edge(clk) then
if input1 = '1' then
if input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

C. if rising_edge(clk) then
if input1 = '1' or input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

D. if rising_edge(clk) then
if input1 = '1' and input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

Solution

1. Step 1: Understand the condition

   Output should be '1' only if input1 = '1' AND input2 = '0'. Otherwise, output is '0'.

2. Step 2: Check each option's logic and syntax

   if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1'; else output <= '0'; end if; end if; correctly uses 'and' and proper if-then-else with semicolons. if rising_edge(clk) then if input1 = '1' then if input2 = '0' then output <= '1'; else output <= '0'; end if; end if; misses end if; for the rising_edge if. if rising_edge(clk) then if input1 = '1' or input2 = '0' then output <= '1'; else output <= '0'; end if; end if; uses 'or' instead of 'and'. if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1' else output <= '0'; end if; end if; misses semicolon after output <= '1'.

3. Final Answer:

   if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1'; else output <= '0'; end if; end if; -> Option D

4. Quick Check:

   Use 'and' for both conditions and end statements with semicolons [OK]

Hint: Use 'and' for both conditions and end lines with semicolons [OK]

Common Mistakes:

• Using 'or' instead of 'and' for conditions
• Missing semicolons after assignments
• Not closing nested if statements properly