If-then-else in process in VHDL - Mini Project: Build & Apply

If-then-else in process

📖 Scenario: You are designing a simple digital circuit that controls an LED based on a switch input. The LED should turn on when the switch is pressed and turn off when it is not pressed.

🎯 Goal: Build a VHDL process using if-then-else statements to control an LED output based on a switch input.

📋 What You'll Learn

Create a signal called switch representing the input switch.

Create a signal called led representing the LED output.

Use a process block triggered by switch.

Inside the process, use if-then-else to set led to '1' when switch is '1', else '0'.

Print the value of led after the process.

💡 Why This Matters

🌍 Real World

Controlling LEDs or other outputs based on input switches is common in embedded systems and digital electronics.

💼 Career

Understanding VHDL processes and conditional statements is essential for FPGA and ASIC design engineers.

1

Create signals for switch and led

Create a signal called switch of type std_logic and set it to '0'. Also create a signal called led of type std_logic and set it to '0'.

VHDL

signal switch : std_logic := '0';
signal led : std_logic := '0';
-- Your code here

Hint

Use signal keyword to declare signals and assign initial values with :=

2

Create a process triggered by switch

Create a process block that is sensitive to the signal switch.

VHDL

signal switch : std_logic := '0';
signal led : std_logic := '0';

process(switch)
begin
    -- Your code here
end process;

Hint

Use process(switch) to start the process and end process; to end it.

3

Add if-then-else inside the process

Inside the process, write an if statement that checks if switch = '1'. If true, set led <= '1', else set led <= '0'.

VHDL

signal switch : std_logic := '0';
signal led : std_logic := '0';

process(switch)
begin
    -- Your code here
end process;

Hint

Use if ... then ... else ... end if; syntax inside the process.

4

Print the led signal value

Write a statement to print the value of led using report statement.

VHDL

signal switch : std_logic := '0';
signal led : std_logic := '0';

process(switch)
begin
    if switch = '1' then
        led <= '1';
    else
        led <= '0';
    end if;
end process;

-- Your code here

Hint

Use report to display messages in VHDL simulation.

Practice

1. What is the main purpose of using if-then-else inside a VHDL process?

easy

A. To specify the clock frequency

B. To declare new signals

C. To choose different actions based on conditions

D. To define the entity interface

Solution

1. Step 1: Understand the role of if-then-else in VHDL process

   The if-then-else statement allows the process to select different actions depending on the condition evaluated.

2. Step 2: Compare other options

   Declaring signals, defining entity interface, and specifying clock frequency are unrelated to if-then-else usage inside a process.

3. Final Answer:

   To choose different actions based on conditions -> Option C

4. Quick Check:

   If-then-else controls actions by conditions [OK]

Hint: If-then-else picks actions based on conditions [OK]

Common Mistakes:

• Confusing if-then-else with signal declaration
• Thinking if-then-else defines entity ports
• Assuming it sets clock frequency

2. Which of the following is the correct syntax for an if-then-else statement inside a VHDL process?

easy

A. if (condition) { signal = '1'; } else { signal = '0'; }

B. if condition then signal <= '1'; else signal <= '0'; end if;

C. if condition: signal = '1' else signal = '0'

D. if condition then signal = 1 else signal = 0 end if

Solution

1. Step 1: Review VHDL if-then-else syntax

   VHDL uses 'if condition then ... else ... end if;' with signal assignment using '<=' and single quotes for bits.

2. Step 2: Check each option

   if condition then signal <= '1'; else signal <= '0'; end if; matches correct syntax. Options B and C use other languages' syntax. if condition then signal = 1 else signal = 0 end if misses semicolons and uses '=' instead of '<='.

3. Final Answer:

   if condition then signal <= '1'; else signal <= '0'; end if; -> Option B

4. Quick Check:

   VHDL if-then-else uses 'then', '<=', and 'end if;' [OK]

Hint: VHDL uses 'then', '<=', and ends with 'end if;' [OK]

Common Mistakes:

• Using curly braces or parentheses like other languages
• Using '=' instead of '<=' for signal assignment
• Omitting semicolons or 'end if;'

3. Consider the following VHDL process:

process(clk)
begin
  if rising_edge(clk) then
    if input = '1' then
      output <= '0';
    else
      output <= '1';
    end if;
  end if;
end process;

What will be the value of output after a rising clock edge if input is '1'?

medium

A. '0'

B. Undefined

C. '1'

D. 'Z'

Solution

1. Step 1: Analyze the process on rising clock edge

   When clk rises, the process checks if input = '1'. If true, output is assigned '0'.

2. Step 2: Apply input value '1'

   Since input = '1', output <= '0' is executed.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Input '1' sets output to '0' [OK]

Hint: Check condition inside rising_edge block carefully [OK]

Common Mistakes:

• Ignoring the nested if condition
• Confusing output with input value
• Assuming output stays unchanged

4. Identify the error in this VHDL process:

process(clk)
begin
  if clk'event and clk = '1' then
    if input = '1' then
      output <= '1'
    else
      output <= '0';
    end if;
  end if;
end process;

medium

A. Missing semicolon after output <= '1'

B. Wrong sensitivity list

C. Incorrect use of clk'event

D. Missing end if; for outer if

Solution

1. Step 1: Check each statement for syntax errors

   Inside the inner if, the line output <= '1' lacks a semicolon at the end.

2. Step 2: Verify other parts

   Sensitivity list includes clk, which is correct. clk'event and clk = '1' is valid for rising edge detection. The outer if has matching end if;.

3. Final Answer:

   Missing semicolon after output <= '1' -> Option A

4. Quick Check:

   Every statement must end with semicolon [OK]

Hint: Check semicolons after every assignment line [OK]

Common Mistakes:

• Forgetting semicolon after signal assignment
• Confusing clk'event with rising_edge(clk)
• Missing end if for if statements

5. You want to design a VHDL process that sets output to '1' if input1 is '1' and input2 is '0', otherwise sets output to '0'. Which is the correct if-then-else structure inside a clocked process?

hard

A. if rising_edge(clk) then
if input1 = '1' and input2 = '0' then
output <= '1'
else
output <= '0';
end if;
end if;

B. if rising_edge(clk) then
if input1 = '1' then
if input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

C. if rising_edge(clk) then
if input1 = '1' or input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

D. if rising_edge(clk) then
if input1 = '1' and input2 = '0' then
output <= '1';
else
output <= '0';
end if;
end if;

Solution

1. Step 1: Understand the condition

   Output should be '1' only if input1 = '1' AND input2 = '0'. Otherwise, output is '0'.

2. Step 2: Check each option's logic and syntax

   if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1'; else output <= '0'; end if; end if; correctly uses 'and' and proper if-then-else with semicolons. if rising_edge(clk) then if input1 = '1' then if input2 = '0' then output <= '1'; else output <= '0'; end if; end if; misses end if; for the rising_edge if. if rising_edge(clk) then if input1 = '1' or input2 = '0' then output <= '1'; else output <= '0'; end if; end if; uses 'or' instead of 'and'. if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1' else output <= '0'; end if; end if; misses semicolon after output <= '1'.

3. Final Answer:

   if rising_edge(clk) then if input1 = '1' and input2 = '0' then output <= '1'; else output <= '0'; end if; end if; -> Option D

4. Quick Check:

   Use 'and' for both conditions and end statements with semicolons [OK]

Hint: Use 'and' for both conditions and end lines with semicolons [OK]

Common Mistakes:

• Using 'or' instead of 'and' for conditions
• Missing semicolons after assignments
• Not closing nested if statements properly