BCD counter design in VHDL - Step-by-Step Execution

Concept Flow - BCD counter design

Start: Reset counter to 0

↓

Wait for clock rising edge

↓

Check if counter < 9?

No→Reset counter to 0

↓

Output counter

↓

Increment counter by 1

↓

Output current counter value

↓

Repeat

The BCD counter resets to 0, increments on each clock pulse until 9, then resets to 0 again, outputting the current count each time.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
  elsif rising_edge(clk) then
    if count < 9 then
      count <= count + 1;
    else
      count <= 0;
    end if;
  end if;
end process;

This VHDL process increments a BCD counter on each clock rising edge, resetting to 0 after 9 or when reset is active.

Execution Table

Step	reset	clk edge	count before	Condition (count < 9)	Action	count after	Output
1	1	No	X	N/A	Reset active	0	0
2	0	Yes	0	True	Increment count	1	1
3	0	Yes	1	True	Increment count	2	2
4	0	Yes	2	True	Increment count	3	3
5	0	Yes	3	True	Increment count	4	4
6	0	Yes	4	True	Increment count	5	5
7	0	Yes	5	True	Increment count	6	6
8	0	Yes	6	True	Increment count	7	7
9	0	Yes	7	True	Increment count	8	8
10	0	Yes	8	True	Increment count	9	9
11	0	Yes	9	False	Reset count to 0	0	0
12	0	No	0	N/A	No clock edge	0	0

💡 Execution stops or waits when no clock edge or reset is active; counter cycles 0 to 9 repeatedly.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	After 10	After 11	Final
count	X	0	1	2	3	4	5	6	7	8	9	0	0
reset	1	0	0	0	0	0	0	0	0	0	0	0	0
clk edge	No	No	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	Yes	No

Key Moments - 3 Insights

Why does the counter reset to 0 after reaching 9 instead of continuing to 10?

Because the condition 'count < 9' becomes false at 9 (see step 11 in execution_table), triggering the else branch that resets count to 0.

What happens if the reset signal is active during a clock edge?

The reset condition has priority (step 1), so the counter is set to 0 immediately regardless of the clock edge or count value.

Why does the counter not change when there is no clock edge?

Because the process only updates count on the rising edge of clk (see step 12), so without a clock edge, count remains the same.

Visual Quiz - 3 Questions

Look at the execution_table at step 10, what is the value of count after the clock edge?

A 8

B 9

C 0

D 10

💡 Hint

Check the 'count after' column at step 10 in the execution_table.

At which step does the condition 'count < 9' become false?

A Step 11

B Step 10

C Step 9

D Step 12

💡 Hint

Look at the 'Condition (count < 9)' column in the execution_table.

If reset is active at step 2, what would be the count after that step?

A 1

B 2

C 0

D Undefined

💡 Hint

Refer to step 1 where reset is active and count is set to 0.

Concept Snapshot

VHDL BCD Counter:
- On reset, count <= 0
- On rising clock edge:
  if count < 9 then count <= count + 1
  else count <= 0
- Outputs count 0 to 9 repeatedly
- Reset has highest priority
- Counts only on clock rising edge

Full Transcript

This VHDL BCD counter design uses a process triggered by clock and reset signals. When reset is active, the counter resets to zero immediately. On each rising edge of the clock, if the count is less than 9, it increments by one; otherwise, it resets to zero. The counter outputs values from 0 to 9 repeatedly. The execution table shows step-by-step how the count changes with each clock pulse and reset signal. Key moments clarify why the counter resets after 9, the priority of reset, and behavior when no clock edge occurs. The visual quiz tests understanding of count values at specific steps and the effect of reset.

Practice

1. What is the main function of a BCD counter in digital circuits?

easy

A. To count decimal digits from 0 to 9 in binary form

B. To count binary numbers from 0 to 15

C. To convert analog signals to digital

D. To multiply two binary numbers

Solution

1. Step 1: Understand BCD counting

   A BCD counter counts decimal digits 0 through 9 using binary representation.

2. Step 2: Differentiate from binary counters

   Unlike a binary counter that counts up to 15 (4 bits), BCD resets after 9 to represent decimal digits.

3. Final Answer:

   To count decimal digits from 0 to 9 in binary form -> Option A

4. Quick Check:

   BCD counter counts 0-9 decimal digits [OK]

Hint: BCD counters count decimal digits 0-9 in binary [OK]

Common Mistakes:

• Confusing BCD with binary counters counting 0-15
• Thinking BCD converts analog signals
• Assuming BCD performs arithmetic multiplication

2. Which of the following is the correct VHDL syntax to declare a 4-bit signal named count for a BCD counter?

easy

A. signal count : integer range 0 to 15;

B. signal count : std_logic_vector(3 to 0);

C. signal count : bit_vector(3 to 0);

D. signal count : std_logic_vector(3 downto 0);

Solution

1. Step 1: Identify correct vector type and range

   For a 4-bit signal, std_logic_vector(3 downto 0) is standard and correct.

2. Step 2: Check other options for errors

   Integer range 0 to 15 uses integer type, not vector; bit_vector(3 to 0) uses invalid range direction; std_logic_vector(3 to 0) uses invalid range direction.

3. Final Answer:

   signal count : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   4-bit std_logic_vector with downto 0 indexing [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit signals [OK]

Common Mistakes:

• Using integer instead of std_logic_vector for bit signals
• Incorrect vector range direction
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a BCD counter, what will be the value of count after the 10th rising clock edge?

process(clk)
begin
  if rising_edge(clk) then
    if count = "1001" then
      count <= "0000";
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. "1010"

B. "0000"

C. "1001"

D. "0001"

Solution

1. Step 1: Understand counting behavior

   The counter increments each clock edge until it reaches "1001" (decimal 9), then resets to "0000".

2. Step 2: Count 10 clock edges

   After 9 increments, count is "1001"; on the 10th clock, it resets to "0000".

3. Final Answer:

   "0000" -> Option B

4. Quick Check:

   BCD resets after 9, so 10th count is 0 [OK]

Hint: BCD resets to 0 after 9 counts [OK]

Common Mistakes:

• Assuming count continues to "1010" which is invalid BCD
• Forgetting reset condition at 9
• Confusing binary and decimal counting

4. Identify the error in this VHDL BCD counter snippet:

process(clk)
begin
  if rising_edge(clk) then
    if count = "1010" then
      count <= "0000";
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. The process is missing a sensitivity list

B. The signal count is not declared

C. The reset condition should check for "1001" instead of "1010"

D. The increment operation is invalid for std_logic_vector

Solution

1. Step 1: Check reset condition value

   BCD counts 0 to 9, so reset should occur at "1001" (decimal 9), not "1010" (decimal 10).

2. Step 2: Verify other parts

   Signal declaration and sensitivity list are correct; increment on std_logic_vector requires numeric conversion but is often handled by libraries.

3. Final Answer:

   The reset condition should check for "1001" instead of "1010" -> Option C

4. Quick Check:

   BCD resets at 9 ("1001"), not 10 ("1010") [OK]

Hint: Reset BCD at "1001" (decimal 9), not "1010" [OK]

Common Mistakes:

• Using "1010" as reset condition instead of "1001"
• Ignoring numeric conversion for increment
• Confusing sensitivity list requirements

5. You want to design a BCD counter in VHDL that counts from 0 to 9 and then resets to 0. Which approach correctly implements this behavior?

hard

A. Use a 4-bit std_logic_vector, increment it each clock, and reset to "0000" when it reaches "1001"

B. Use an integer signal from 0 to 15 and reset at 9

C. Use a 4-bit std_logic_vector and reset at "1111"

D. Use a 3-bit std_logic_vector and reset at "1001"

Solution

1. Step 1: Choose correct signal type and size

   A 4-bit std_logic_vector is needed to represent digits 0 to 9 in BCD.

2. Step 2: Implement correct reset condition

   Reset should occur when count reaches "1001" (decimal 9), then reset to "0000" to repeat counting.

3. Final Answer:

   Use a 4-bit std_logic_vector, increment it each clock, and reset to "0000" when it reaches "1001" -> Option A

4. Quick Check:

   4-bit vector + reset at 9 = correct BCD counter [OK]

Hint: Use 4-bit vector and reset at "1001" for BCD [OK]

Common Mistakes:

• Using integer range 0-15 instead of 0-9
• Resetting at wrong binary value like "1111"
• Using 3-bit vector which can't hold 0-9