BCD counter design in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple BCD counter process

What is the output value of the signal count after 12 clock cycles in the following BCD counter process?

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity bcd_counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR (3 downto 0));
end bcd_counter;

architecture Behavioral of bcd_counter is
    signal cnt : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            cnt <= (others => '0');
        elsif rising_edge(clk) then
            if cnt = to_unsigned(9, 4) then
                cnt <= (others => '0');
            else
                cnt <= cnt + 1;
            end if;
        end if;
    end process;
    count <= std_logic_vector(cnt);
end Behavioral;

A "0010" (2 in decimal)

B "0011" (3 in decimal)

C "0000" (0 in decimal)

D "0011" (11 in decimal, invalid BCD)

💡 Hint

Remember the counter resets to 0 after reaching 9.

The counter increments from 0 to 9 and then resets. After 12 clock cycles, it counts 0 to 9 (10 cycles), then 0 and 1 for the next two cycles, so the count is 2 (binary 0010).

🧠 Conceptual

intermediate

Understanding BCD counter reset behavior

In a BCD counter implemented in VHDL, what is the main reason for resetting the count to 0 when the count reaches 9?

A To synchronize the counter with the clock signal

B To save power by stopping the counter

C To prevent the counter from exceeding the decimal digit range 0-9

D To avoid overflow in the 4-bit binary representation

💡 Hint

Think about what decimal digits a BCD counter should represent.

A BCD counter counts decimal digits 0 through 9. Resetting at 9 ensures the counter stays within valid decimal digit range.

🔧 Debug

advanced

Identify the error in this BCD counter code snippet

What error will occur when running this VHDL BCD counter code?

VHDL

process(clk, reset)
begin
    if reset = '1' then
        cnt <= (others => '0');
    elsif rising_edge(clk) then
        if cnt = 10 then
            cnt <= (others => '0');
        else
            cnt <= cnt + 1;
        end if;
    end if;
end process;

A Runtime error: counter will overflow

B No error, code runs correctly

C Syntax error due to missing semicolon

D Comparison error: 'cnt = 10' is invalid for unsigned(3 downto 0)

💡 Hint

Check the data type and value used in the comparison.

The signal 'cnt' is unsigned(3 downto 0), so comparing it to integer 10 directly is invalid. It should be compared to unsigned("1010") or converted properly.

📝 Syntax

advanced

Syntax error in BCD counter process

Which option contains the correct syntax to increment a 4-bit unsigned BCD counter in VHDL?

VHDL

process(clk, reset)
begin
    if reset = '1' then
        cnt <= (others => '0');
    elsif rising_edge(clk) then
        -- increment logic here
    end if;
end process;

A if cnt = to_unsigned(9, 4) then cnt <= (others => '0'); else cnt <= cnt + 1; end if;

B if cnt = "1001" then cnt <= (others => '0'); else cnt <= cnt + 1; end if;

C if cnt = 9 then cnt <= 0; else cnt <= cnt + 1; end if;

D if cnt = 9 then cnt <= (others => '0'); else cnt <= cnt + 1; end if;

💡 Hint

Consider the data type of 'cnt' and how to compare it properly.

Since 'cnt' is unsigned(3 downto 0), it must be compared to an unsigned value. Option A uses 'to_unsigned(9,4)' which is correct syntax.

🚀 Application

expert

Design challenge: Extending a BCD counter to count from 0 to 59

You want to design a VHDL counter that counts from 0 to 59 in BCD format (two digits). Which approach correctly implements this?

A Use a single 6-bit unsigned counter counting 0 to 59 and convert to BCD for output

B Use two 4-bit unsigned counters, one for units (0-9) and one for tens (0-5), increment units every clock, reset units and increment tens when units reach 9, reset tens when it reaches 5

C Use two 4-bit counters both counting 0 to 9 independently and reset both at 59

D Use a 7-bit unsigned counter counting 0 to 59 and output the lower 4 bits as units and upper 3 bits as tens

💡 Hint

Think about how BCD digits represent decimal numbers and how to handle carry between digits.

BCD counting from 0 to 59 requires two digits: units (0-9) and tens (0-5). Increment units each clock, and when units reach 9, reset units and increment tens. Tens resets at 5.

Practice

1. What is the main function of a BCD counter in digital circuits?

easy

A. To count decimal digits from 0 to 9 in binary form

B. To count binary numbers from 0 to 15

C. To convert analog signals to digital

D. To multiply two binary numbers

Solution

1. Step 1: Understand BCD counting

   A BCD counter counts decimal digits 0 through 9 using binary representation.

2. Step 2: Differentiate from binary counters

   Unlike a binary counter that counts up to 15 (4 bits), BCD resets after 9 to represent decimal digits.

3. Final Answer:

   To count decimal digits from 0 to 9 in binary form -> Option A

4. Quick Check:

   BCD counter counts 0-9 decimal digits [OK]

Hint: BCD counters count decimal digits 0-9 in binary [OK]

Common Mistakes:

• Confusing BCD with binary counters counting 0-15
• Thinking BCD converts analog signals
• Assuming BCD performs arithmetic multiplication

2. Which of the following is the correct VHDL syntax to declare a 4-bit signal named count for a BCD counter?

easy

A. signal count : integer range 0 to 15;

B. signal count : std_logic_vector(3 to 0);

C. signal count : bit_vector(3 to 0);

D. signal count : std_logic_vector(3 downto 0);

Solution

1. Step 1: Identify correct vector type and range

   For a 4-bit signal, std_logic_vector(3 downto 0) is standard and correct.

2. Step 2: Check other options for errors

   Integer range 0 to 15 uses integer type, not vector; bit_vector(3 to 0) uses invalid range direction; std_logic_vector(3 to 0) uses invalid range direction.

3. Final Answer:

   signal count : std_logic_vector(3 downto 0); -> Option D

4. Quick Check:

   4-bit std_logic_vector with downto 0 indexing [OK]

Hint: Use std_logic_vector(3 downto 0) for 4-bit signals [OK]

Common Mistakes:

• Using integer instead of std_logic_vector for bit signals
• Incorrect vector range direction
• Using bit_vector instead of std_logic_vector

3. Given the following VHDL process for a BCD counter, what will be the value of count after the 10th rising clock edge?

process(clk)
begin
  if rising_edge(clk) then
    if count = "1001" then
      count <= "0000";
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. "1010"

B. "0000"

C. "1001"

D. "0001"

Solution

1. Step 1: Understand counting behavior

   The counter increments each clock edge until it reaches "1001" (decimal 9), then resets to "0000".

2. Step 2: Count 10 clock edges

   After 9 increments, count is "1001"; on the 10th clock, it resets to "0000".

3. Final Answer:

   "0000" -> Option B

4. Quick Check:

   BCD resets after 9, so 10th count is 0 [OK]

Hint: BCD resets to 0 after 9 counts [OK]

Common Mistakes:

• Assuming count continues to "1010" which is invalid BCD
• Forgetting reset condition at 9
• Confusing binary and decimal counting

4. Identify the error in this VHDL BCD counter snippet:

process(clk)
begin
  if rising_edge(clk) then
    if count = "1010" then
      count <= "0000";
    else
      count <= count + 1;
    end if;
  end if;
end process;

medium

A. The process is missing a sensitivity list

B. The signal count is not declared

C. The reset condition should check for "1001" instead of "1010"

D. The increment operation is invalid for std_logic_vector

Solution

1. Step 1: Check reset condition value

   BCD counts 0 to 9, so reset should occur at "1001" (decimal 9), not "1010" (decimal 10).

2. Step 2: Verify other parts

   Signal declaration and sensitivity list are correct; increment on std_logic_vector requires numeric conversion but is often handled by libraries.

3. Final Answer:

   The reset condition should check for "1001" instead of "1010" -> Option C

4. Quick Check:

   BCD resets at 9 ("1001"), not 10 ("1010") [OK]

Hint: Reset BCD at "1001" (decimal 9), not "1010" [OK]

Common Mistakes:

• Using "1010" as reset condition instead of "1001"
• Ignoring numeric conversion for increment
• Confusing sensitivity list requirements

5. You want to design a BCD counter in VHDL that counts from 0 to 9 and then resets to 0. Which approach correctly implements this behavior?

hard

A. Use a 4-bit std_logic_vector, increment it each clock, and reset to "0000" when it reaches "1001"

B. Use an integer signal from 0 to 15 and reset at 9

C. Use a 4-bit std_logic_vector and reset at "1111"

D. Use a 3-bit std_logic_vector and reset at "1001"

Solution

1. Step 1: Choose correct signal type and size

   A 4-bit std_logic_vector is needed to represent digits 0 to 9 in BCD.

2. Step 2: Implement correct reset condition

   Reset should occur when count reaches "1001" (decimal 9), then reset to "0000" to repeat counting.

3. Final Answer:

   Use a 4-bit std_logic_vector, increment it each clock, and reset to "0000" when it reaches "1001" -> Option A

4. Quick Check:

   4-bit vector + reset at 9 = correct BCD counter [OK]

Hint: Use 4-bit vector and reset at "1001" for BCD [OK]

Common Mistakes:

• Using integer range 0-15 instead of 0-9
• Resetting at wrong binary value like "1111"
• Using 3-bit vector which can't hold 0-9