Why memory blocks store data in digital systems in VHDL - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a memory block with 8 locations.

VHDL

type memory_array is array (0 to 7) of std_logic_vector(7 downto 0);
signal memory : memory_array := (others => (others => '0'));
-- Memory has [1] locations

Drag options to blanks, or click blank then click option'

A16

B8

C4

D32

Attempts:

3 left

💡 Hint

Common Mistakes

Confusing the range endpoints with the number of locations.

The memory block is declared with 8 locations indexed from 0 to 7.

2fill in blank

medium

Complete the code to read data from memory at address 'addr'.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    data_out <= memory([1]);
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Breset

Caddr

Ddata_in

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_in or clk instead of the address signal.

The address signal 'addr' is used to index the memory for reading data.

3fill in blank

hard

Fix the error in the write process to store data on rising clock edge.

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if write_enable = '1' then
      memory([1]) <= data_in;
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aaddr

Bdata_out

Cwrite_enable

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using data_out or write_enable as the memory index.

The address signal 'addr' specifies where to write the input data in memory.

4fill in blank

hard

Fill both blanks to create a memory block with 16 locations and 8-bit width.

VHDL

type memory_array is array (0 to [1]) of std_logic_vector([2] downto 0);
signal memory : memory_array;

Drag options to blanks, or click blank then click option'

A15

B7

C8

D16

Attempts:

3 left

💡 Hint

Common Mistakes

Using 16 as upper index instead of 15.

Using 8 downto 0 for 8 bits instead of 7 downto 0.

The memory has 16 locations indexed 0 to 15, and each location is 8 bits wide (7 downto 0).

5fill in blank

hard

Fill all three blanks to write data to memory only when write_enable is active and clock rises.

VHDL

process([1])
begin
  if rising_edge([2]) then
    if [3] = '1' then
      memory(addr) <= data_in;
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclk

Bwrite_enable

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset instead of clk in sensitivity list or rising_edge.

Checking wrong signal instead of write_enable.

The process is sensitive to 'clk', the rising edge of 'clk' triggers the write, and 'write_enable' controls if data is written.

Practice

1. Why do memory blocks store data in digital systems?

easy

A. To remember information for later use

B. To perform calculations faster

C. To display images on the screen

D. To connect different devices

Solution

1. Step 1: Understand the purpose of memory blocks

   Memory blocks are used to keep data so the system can use it later.

2. Step 2: Identify the main function in digital systems

   Remembering information is essential for processing and decision making.

3. Final Answer:

   To remember information for later use -> Option A

4. Quick Check:

   Memory stores data = Remember information [OK]

Hint: Memory means storing data to use later [OK]

Common Mistakes:

• Confusing memory with processing speed
• Thinking memory displays output
• Assuming memory connects devices

2. Which VHDL syntax correctly declares a memory block of 8 bits?

easy

A. signal mem : std_logic_vector(7 downto 0);

B. signal mem : integer range 0 to 7;

C. variable mem : std_logic;

D. constant mem : std_logic_vector(0 to 7);

Solution

1. Step 1: Identify correct VHDL syntax for memory signals

   Memory blocks are often declared as signals with std_logic_vector type for bits.

2. Step 2: Check the range and type

   std_logic_vector(7 downto 0) defines 8 bits indexed from 7 down to 0, which is standard.

3. Final Answer:

   signal mem : std_logic_vector(7 downto 0); -> Option A

4. Quick Check:

   std_logic_vector with 8 bits = correct memory declaration [OK]

Hint: Use std_logic_vector with downto for bit arrays [OK]

Common Mistakes:

• Using integer instead of std_logic_vector
• Declaring variable instead of signal for memory
• Using constant instead of signal for writable memory

3. What is the output of this VHDL process storing data in a memory block?

signal mem : std_logic_vector(3 downto 0);
begin
  mem <= "1010";
  wait for 10 ns;
  mem <= "1100";
end process;

What is the value of mem after 15 ns?

medium

A. "1010"

B. "1111"

C. "1100"

D. "0000"

Solution

1. Step 1: Analyze the timing of assignments

   At start, mem is assigned "1010". After 10 ns, mem is assigned "1100".

2. Step 2: Determine mem value at 15 ns

   Since 15 ns is after 10 ns, mem holds the second value "1100".

3. Final Answer:

   "1100" -> Option C

4. Quick Check:

   After 10 ns assignment, mem = "1100" [OK]

Hint: Later assignment overwrites earlier after wait [OK]

Common Mistakes:

• Ignoring the wait time and choosing first value
• Assuming mem resets to zero
• Confusing bit patterns

4. Identify the error in this VHDL memory block declaration:

signal memory : std_logic_vector(0 to 7);
memory(8) <= '1';

medium

A. std_logic_vector cannot be used for memory

B. Index 8 is out of range for memory

C. signal keyword is missing

D. Assignment operator <= is incorrect

Solution

1. Step 1: Check the declared range of memory

   Memory is declared from index 0 to 7, so valid indices are 0 through 7.

2. Step 2: Check the assignment index

   Assigning to memory(8) is invalid because index 8 is outside the declared range.

3. Final Answer:

   Index 8 is out of range for memory -> Option B

4. Quick Check:

   Index must be within 0 to 7 [OK]

Hint: Check index range matches declared vector bounds [OK]

Common Mistakes:

• Assuming index 8 is valid
• Confusing signal declaration with variable
• Thinking assignment operator is wrong

5. How can you implement a simple 4-word memory block in VHDL that stores 8-bit data and allows reading by address?

hard

A. Use integer signals to store data without indexing

B. Declare four separate std_logic signals and assign them manually

C. Use a single std_logic_vector(31 downto 0) without addressing

D. Use an array of std_logic_vector(7 downto 0) indexed by 2-bit address signal

Solution

1. Step 1: Understand memory structure requirements

   A 4-word memory with 8-bit data needs an array of 4 elements, each 8 bits wide.

2. Step 2: Choose correct VHDL type and indexing

   Use an array type like array(0 to 3) of std_logic_vector(7 downto 0), indexed by a 2-bit address signal.

3. Final Answer:

   Use an array of std_logic_vector(7 downto 0) indexed by 2-bit address signal -> Option D

4. Quick Check:

   Array + address signal = memory block [OK]

Hint: Memory = array indexed by address signal [OK]

Common Mistakes:

• Using separate signals instead of array
• Ignoring address indexing
• Using integer signals without indexing