Challenge - 5 Problems
VHDL Generate Master
Get all challenges correct to earn this badge!
Test your skills under time pressure!
❓ Predict Output
intermediate2:00remaining
Output of a simple generate loop
What is the output of the following VHDL code snippet when simulated for 4 clock cycles?
architecture Behavioral of test is
signal leds : std_logic_vector(3 downto 0);
begin
gen_leds: for i in 0 to 3 generate
begin
process
begin
leds(i) <= '1';
wait for 10 ns;
leds(i) <= '0';
wait for 10 ns;
end process;
end generate gen_leds;
end Behavioral;VHDL
architecture Behavioral of test is signal leds : std_logic_vector(3 downto 0); begin gen_leds: for i in 0 to 3 generate begin process begin leds(i) <= '1'; wait for 10 ns; leds(i) <= '0'; wait for 10 ns; end process; end generate gen_leds; end Behavioral;
Attempts:
2 left
💡 Hint
Consider how the generate statement creates multiple processes, each controlling one bit of leds.
✗ Incorrect
The generate loop creates four separate processes, each toggling one bit of the leds vector independently every 20 ns. Since all start simultaneously, all bits blink together.
❓ Predict Output
intermediate2:00remaining
Value of signal after generate block
Given the following VHDL code, what is the value of the signal
out_vec after elaboration?architecture Behavioral of test is
signal out_vec : std_logic_vector(7 downto 0) := (others => '0');
begin
gen_bits: for i in 0 to 7 generate
begin
out_vec(i) <= '1' when i mod 2 = 0 else '0';
end generate gen_bits;
end Behavioral;VHDL
architecture Behavioral of test is signal out_vec : std_logic_vector(7 downto 0) := (others => '0'); begin gen_bits: for i in 0 to 7 generate begin out_vec(i) <= '1' when i mod 2 = 0 else '0'; end generate gen_bits; end Behavioral;
Attempts:
2 left
💡 Hint
Remember that VHDL vectors are indexed from left to right as (7 downto 0).
✗ Incorrect
The generate loop assigns '1' to even indices and '0' to odd indices. Since bit 0 is the least significant bit, out_vec = "01010101" with bit 0 = '1'.
🔧 Debug
advanced2:00remaining
Identify the error in generate statement
What error will the following VHDL code produce?
architecture Behavioral of test is
signal data : std_logic_vector(3 downto 0);
begin
gen_loop: for i in 0 to 4 generate
begin
data(i) <= '1';
end generate gen_loop;
end Behavioral;VHDL
architecture Behavioral of test is signal data : std_logic_vector(3 downto 0); begin gen_loop: for i in 0 to 4 generate begin data(i) <= '1'; end generate gen_loop; end Behavioral;
Attempts:
2 left
💡 Hint
Check the range of the signal and the generate loop index.
✗ Incorrect
The signal 'data' has indices 3 downto 0 (4 bits), but the generate loop runs from 0 to 4 (5 iterations). Accessing data(4) is out of range causing an index error.
📝 Syntax
advanced2:00remaining
Correct syntax for generate statement
Which option shows the correct syntax for a generate statement that creates 8 instances of a component named
my_comp with generic id set to the loop index?Attempts:
2 left
💡 Hint
Check the use of '=>' in generic map and the presence of 'end generate' with label.
✗ Incorrect
Option B uses correct syntax: '=>' for generic map, parentheses for port map, and ends with 'end generate' plus label.
🚀 Application
expert2:00remaining
Number of signals generated by nested generate statements
Consider the following nested generate statements in VHDL:
How many individual signal assignments are created by these generate statements?
architecture Behavioral of test is
signal matrix : std_logic_vector(15 downto 0);
begin
gen_row: for r in 0 to 3 generate
gen_col: for c in 0 to 3 generate
matrix(r*4 + c) <= '1';
end generate gen_col;
end generate gen_row;
end Behavioral;How many individual signal assignments are created by these generate statements?
Attempts:
2 left
💡 Hint
Multiply the number of iterations of the outer and inner generate loops.
✗ Incorrect
The outer loop runs 4 times (0 to 3), inner loop runs 4 times (0 to 3), total assignments = 4 * 4 = 16.