Dual-port RAM design in VHDL - Step-by-Step Execution

Concept Flow - Dual-port RAM design

Start

↓

Write Port

↓

Write Data to RAM at Write Address

↓

Read Port

↓

Output Read Data

↓

End

The design has two ports: one for writing data to RAM and one for reading data from RAM simultaneously.

Execution Sample

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dual_port_ram is
  port(
    clk : in std_logic;
    we  : in std_logic;
    waddr : in unsigned(3 downto 0);
    din : in std_logic_vector(7 downto 0);
    raddr : in unsigned(3 downto 0);
    dout : out std_logic_vector(7 downto 0)
  );
end entity;

architecture rtl of dual_port_ram is
  type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);
  signal ram : ram_type := (others => (others => '0'));
begin
  process(clk)
  begin
    if rising_edge(clk) then
      if we = '1' then
        ram(to_integer(waddr)) <= din;
      end if;
      dout <= ram(to_integer(raddr));
    end if;
  end process;
end rtl;

This VHDL code defines a 16x8-bit dual-port RAM with separate read and write addresses and a write enable signal.

Execution Table

Step	clk edge	we	waddr	din	raddr	Action	RAM State at waddr	dout Output
1	rising	0	0001	00000001	0000	No write, read from addr 0	00000000	00000000
2	rising	1	0010	00000010	0001	Write din to addr 2, read addr 1	00000010	00000000
3	rising	1	0001	00000101	0010	Write din to addr 1, read addr 2	00000101	00000010
4	rising	0	xxxx	xxxxxxxx	0001	No write, read addr 1	00000101	00000101
5	rising	1	0011	00001000	0011	Write din to addr 3, read addr 3 (old data)	00001000	00000000
6	rising	0	xxxx	xxxxxxxx	0010	No write, read addr 2	00001000	00000010
7	rising	0	xxxx	xxxxxxxx	0100	No write, read addr 4	00001000	00000000
Exit	-	-	-	-	-	Simulation ends	-	-

💡 Simulation ends after 7 clock cycles; no more inputs.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7
we	0	0	1	1	0	1	0	0
waddr	0001	0001	0010	0001	xxxx	0011	xxxx	xxxx
din	00000001	00000001	00000010	00000101	xxxxxxxx	00001000	xxxxxxxx	xxxxxxxx
raddr	0000	0000	0001	0010	0001	0011	0010	0100
dout	00000000	00000000	00000000	00000010	00000101	00000000	00000010	00000000
ram[1]	00000000	00000000	00000000	00000101	00000101	00000101	00000101	00000101
ram[2]	00000000	00000000	00000010	00000010	00000010	00000010	00000010	00000010
ram[3]	00000000	00000000	00000000	00000000	00000000	00001000	00001000	00001000

Key Moments - 3 Insights

Why does dout update even when we=0 (no write)?

Because dout always reads the RAM at raddr on every clock rising edge, independent of write enable, as shown in rows 1 and 4 of the execution_table.

What happens if waddr and raddr are the same during a write?

dout shows the old data from the RAM at that address, because the read assignment samples the RAM value before the conditional write updates it. The new data is available for reading from the next clock cycle. In step 5, dout = "00000000" (old), RAM updated to "00001000".

Why is waddr 'xxxx' in some steps?

In those steps, no write occurs (we=0), so waddr and din inputs are ignored; 'xxxx' means don't care or undefined for write inputs.

Visual Quiz - 3 Questions

Look at the execution_table at step 3: what is the value of dout?

A 00000101

B 00000010

C 00000000

D 00001000

💡 Hint

Check the 'dout Output' column at step 3 in the execution_table.

At which step does the RAM write the value 00000101 to address 1?

A Step 2

B Step 5

C Step 3

D Step 4

💡 Hint

Look at the 'Action' and 'RAM State at waddr' columns in the execution_table.

If we change we to '1' at step 1, what will dout be at step 1?

A 00000000

B 00000001

C 00000101

D 00000010

💡 Hint

Even if we=1, dout reads the old data before write takes effect; see variable_tracker for dout values.

Concept Snapshot

Dual-port RAM in VHDL:
- Two ports: one write (we, waddr, din), one read (raddr, dout)
- On clock rising edge:
  * If we=1, write din to RAM[waddr]
  * Always read RAM[raddr] to dout
- Allows simultaneous read and write
- RAM size and data width defined by array and vector sizes

Full Transcript

This visual execution traces a dual-port RAM design in VHDL. The RAM has separate read and write ports allowing simultaneous operations. On each rising clock edge, if the write enable (we) is high, the input data (din) is stored at the write address (waddr). Independently, the output data (dout) always reflects the content at the read address (raddr). The execution table shows step-by-step how inputs affect RAM content and output. The variable tracker records changes in signals and RAM contents over time. Key moments clarify common confusions like why dout updates even without writing, and what happens when read and write addresses match. The quiz tests understanding of RAM behavior at specific steps. The snapshot summarizes the dual-port RAM's key features and operation.

Practice

1. What is the main advantage of using a dual-port RAM in VHDL designs?

easy

A. It simplifies the VHDL code by using only one port.

B. It doubles the memory size automatically.

C. It reduces the clock frequency needed.

D. It allows two independent memory accesses at the same time.

Solution

1. Step 1: Understand dual-port RAM functionality

   Dual-port RAM allows two separate accesses (read or write) simultaneously on different ports.

2. Step 2: Compare options with this feature

   Only 'It allows two independent memory accesses at the same time.' correctly states this advantage; others describe unrelated features.

3. Final Answer:

   It allows two independent memory accesses at the same time. -> Option D

4. Quick Check:

   Dual-port RAM = Two independent accesses [OK]

Hint: Dual-port RAM means two ports can access memory simultaneously [OK]

Common Mistakes:

• Thinking it doubles memory size automatically
• Assuming it reduces clock frequency
• Believing it simplifies code by using one port

2. Which of the following is the correct VHDL port declaration snippet for a dual-port RAM with separate read and write addresses?

easy

A. port(clk : in std_logic; addr : in std_logic_vector(3 downto 0); data : inout std_logic_vector(7 downto 0));

B. port(clk : in std_logic; addr_a : in std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : in std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0));

C. port(clk : in std_logic; addr_a : in std_logic_vector(7 downto 0); data_a : in std_logic_vector(3 downto 0); addr_b : in std_logic_vector(7 downto 0); data_b : in std_logic_vector(3 downto 0));

D. port(clk : in std_logic; addr_a : out std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : out std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0));

Solution

1. Step 1: Identify correct port directions and sizes

   Address ports are inputs, data ports are inout for read/write, clock is input.

2. Step 2: Match with options

   port(clk : in std_logic; addr_a : in std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : in std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0)); correctly declares two address inputs and two data inout ports with proper sizes and directions.

3. Final Answer:

   Port declaration with clk input, separate addr inputs, and data inout ports. -> Option B

4. Quick Check:

   Correct port directions and separate addresses = port(clk : in std_logic; addr_a : in std_logic_vector(3 downto 0); data_a : inout std_logic_vector(7 downto 0); addr_b : in std_logic_vector(3 downto 0); data_b : inout std_logic_vector(7 downto 0)); [OK]

Hint: Addresses are inputs, data ports are inout for dual-port RAM [OK]

Common Mistakes:

• Using addr ports as outputs
• Swapping data and address widths
• Missing separate ports for each RAM port

3. Given this VHDL process snippet for a dual-port RAM, what will be the output on data_b after the rising clock edge if we_a = '1' and addr_a = "0010" with data_a = "10101010"?

process(clk)
begin
  if rising_edge(clk) then
    if we_a = '1' then
      ram(to_integer(unsigned(addr_a))) <= data_a;
    end if;
    data_b <= ram(to_integer(unsigned(addr_b)));
  end if;
end process;

medium

A. Previous data at addr_b only, write does not affect read immediately

B. "10101010" regardless of addr_b

C. "10101010" if addr_b = "0010"; else previous data at addr_b

D. Undefined behavior due to simultaneous read/write

Solution

1. Step 1: Understand signal assignment timing in VHDL processes

   In a clocked process using signals, reads (<=) reflect current values before scheduled updates from this process.

2. Step 2: Trace the execution

   The write schedules ram(addr_a) <= data_a, but data_b <= ram(addr_b) reads the pre-update ram value, so always previous data at addr_b.

3. Final Answer:

   Previous data at addr_b only, write does not affect read immediately -> Option A

4. Quick Check:

   Signal RAM read sees old data before write update [OK]

Hint: VHDL signal RAM: read/write same cycle, read gets old data [OK]

Common Mistakes:

• Thinking write updates immediately for subsequent read in process
• Believing same-address read gets new data
• Assuming undefined behavior for read/write

4. Identify the error in this dual-port RAM VHDL code snippet:

process(clk)
begin
  if rising_edge(clk) then
    if we_a = '1' then
      ram(to_integer(unsigned(addr_a))) <= data_a;
    end if;
    if we_b = '1' then
      ram(to_integer(unsigned(addr_b))) <= data_b;
    end if;
    data_a <= ram(to_integer(unsigned(addr_a)));
    data_b <= ram(to_integer(unsigned(addr_b)));
  end if;
end process;

medium

A. Data ports should be declared as inputs, not outputs.

B. The clock signal is not used correctly in the process sensitivity list.

C. Simultaneous writes to the same RAM without conflict resolution can cause data corruption.

D. The process is missing a reset condition.

Solution

1. Step 1: Analyze simultaneous write conditions

   Both ports can write to RAM at the same clock edge; if addr_a = addr_b, writes conflict without arbitration.

2. Step 2: Check other options

   Clock is correctly used; data ports can be inout; reset is optional but not error here.

3. Final Answer:

   Simultaneous writes to the same RAM without conflict resolution can cause data corruption. -> Option C

4. Quick Check:

   Dual-port RAM needs write conflict handling [OK]

Hint: Check if both ports write same address simultaneously [OK]

Common Mistakes:

• Ignoring write conflicts on same address
• Thinking clock usage is incorrect
• Assuming reset is mandatory for all RAM

5. You need to design a dual-port RAM in VHDL where Port A is write-only and Port B is read-only. Which approach correctly implements this behavior?

hard

A. Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock.

B. Use a single data port for both read and write and control direction with a signal inside the process.

C. Declare both ports as inout and use tri-state buffers to control read/write direction.

D. Use two separate RAM blocks, one for write and one for read, connected externally.

Solution

1. Step 1: Understand port direction requirements

   Port A is write-only, so data port must be input; Port B is read-only, so data port must be output.

2. Step 2: Choose correct implementation

   Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock. matches these requirements with separate addresses and synchronized clock, suitable for dual-port RAM.

3. Final Answer:

   Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock. -> Option A

4. Quick Check:

   Write-only input and read-only output ports = Declare Port A data as input only and Port B data as output only, with separate address inputs and synchronized on the same clock. [OK]

Hint: Match port directions to read/write roles explicitly [OK]

Common Mistakes:

• Using inout ports unnecessarily
• Trying to control direction inside process
• Splitting RAM into two blocks unnecessarily