Design hierarchy best practices in VHDL - Mini Project: Build & Apply

Design Hierarchy Best Practices in VHDL

📖 Scenario: You are designing a simple digital system using VHDL. To keep your design clean and easy to manage, you will create a hierarchy of components. This means you will build small parts first, then combine them into bigger parts.

🎯 Goal: Build a VHDL design with a clear hierarchy by creating a simple AND gate component, then use it inside a top-level module that combines two AND gates.

📋 What You'll Learn

Create a VHDL component for a 2-input AND gate

Declare a signal to connect components

Instantiate two AND gate components in a top-level entity

Print the output signals to verify connections

💡 Why This Matters

🌍 Real World

Design hierarchy helps engineers build complex digital circuits by combining smaller, reusable parts. This makes designs easier to understand and maintain.

💼 Career

Understanding design hierarchy is essential for hardware engineers working with VHDL or other hardware description languages to create scalable and modular digital systems.

1

Create a 2-input AND gate component

Write a VHDL entity and architecture named AndGate with two inputs A and B of type std_logic and one output Y of type std_logic. The output Y should be the AND of inputs A and B.

VHDL

-- Your code here
-- Create entity AndGate with inputs A, B and output Y
-- Implement architecture with Y <= A and B;

Hint

Remember to define the entity with ports and then write the architecture where output Y is assigned the AND of A and B.

2

Declare signals to connect components

In a new VHDL entity named TopLevel, declare two input ports In1 and In2 and one output port Out, all of type std_logic. Inside the architecture, declare a signal named mid_signal of type std_logic to connect the two AND gate components.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y <= A and B;
end Behavioral;

entity TopLevel is
    Port ( In1 : in STD_LOGIC;
           In2 : in STD_LOGIC;
           Out : out STD_LOGIC);
end TopLevel;

architecture Structural of TopLevel is
    signal mid_signal : STD_LOGIC;
    -- Your code here

Hint

Declare the TopLevel entity with ports and inside the architecture declare the signal mid_signal to connect components later.

3

Instantiate two AndGate components in TopLevel

Inside the Structural architecture of TopLevel, instantiate two components of AndGate named and1 and and2. Connect and1 inputs to In1 and In2, output to mid_signal. Connect and2 inputs to mid_signal and In2, output to Out.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AndGate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Y : out STD_LOGIC);
end AndGate;

architecture Behavioral of AndGate is
begin
    Y  In1, B => In2, Y => mid_signal);
    and2 : AndGate port map (A => mid_signal, B => In2, Y => Out);
    -- Your code here
end Structural;

Hint

Use component instantiation syntax with port map to connect signals and ports as described.

4

Print the output signals to verify connections

Write a simple testbench process inside a new entity Testbench that applies values to In1 and In2 signals of TopLevel and prints the output Out to the console using report statements. Show the output for inputs In1 = '1' and In2 = '0'.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Testbench is
end Testbench;

architecture Behavioral of Testbench is
    signal In1 : STD_LOGIC := '0';
    signal In2 : STD_LOGIC := '0';
    signal Out : STD_LOGIC;
begin
    UUT: entity work.TopLevel port map(In1 => In1, In2 => In2, Out => Out);

    process
    begin
        In1 <= '1';
        In2 <= '0';
        wait for 10 ns;
        report "Output Out = " & std_logic'image(Out);
        wait;
    end process;
end Behavioral;

Hint

Use a testbench process to set inputs and use report to print the output signal value.

Practice

1. What is the main purpose of using design hierarchy in VHDL?

easy

A. To increase the clock speed automatically

B. To write all code in a single file

C. To break a large design into smaller, manageable parts

D. To avoid using components

Solution

1. Step 1: Understand design hierarchy concept

   Design hierarchy means dividing a big design into smaller parts for easier management.

2. Step 2: Identify the main purpose

   The main goal is to make complex designs simpler by breaking them down.

3. Final Answer:

   To break a large design into smaller, manageable parts -> Option C

4. Quick Check:

   Design hierarchy = smaller parts [OK]

Hint: Think of big tasks split into small tasks [OK]

Common Mistakes:

• Thinking hierarchy means one big file
• Believing components are avoided
• Assuming clock speed changes automatically

2. Which VHDL keyword is used to declare a reusable block inside a design hierarchy?

easy

A. component

B. process

C. signal

D. variable

Solution

1. Step 1: Recall VHDL keywords for hierarchy

   In VHDL, a reusable block inside a design is declared as a component.

2. Step 2: Differentiate from other keywords

   Process is for sequential code, signal and variable are for data storage, not reusable blocks.

3. Final Answer:

   component -> Option A

4. Quick Check:

   Reusable block = component [OK]

Hint: Components build blocks in hierarchy [OK]

Common Mistakes:

• Confusing process with component
• Using signal or variable as blocks
• Forgetting component declares reusable parts

3. Given this VHDL snippet, what is the correct way to instantiate a component named ALU inside an architecture?

component ALU
  port(
    A, B : in std_logic_vector(3 downto 0);
    Result : out std_logic_vector(3 downto 0)
  );
end component;

-- Inside architecture
U1: ALU port map(
  A => input1,
  B => input2,
  Result => output1
);

medium

A. Correct instantiation with label U1 and port map

B. Missing component declaration before instantiation

C. Port map uses positional mapping instead of named mapping

D. Component name should be lowercase

Solution

1. Step 1: Check component declaration and instantiation

   The component ALU is declared correctly, and instantiation uses label U1 with named port map.

2. Step 2: Verify port map syntax

   Named mapping (A => input1) is valid and clear; component names are case-insensitive but usually uppercase.

3. Final Answer:

   Correct instantiation with label U1 and port map -> Option A

4. Quick Check:

   Component instantiation = label + port map [OK]

Hint: Use label and named port map for clarity [OK]

Common Mistakes:

• Forgetting to declare component before use
• Using positional mapping incorrectly
• Changing component name case unnecessarily

4. Identify the error in this VHDL hierarchy snippet:

component Counter
  port(
    clk : in std_logic;
    count : out integer
  );
end component;

-- Inside architecture
U2: Counter port map(
  clk => clk_signal
);

medium

A. clk_signal is not declared

B. Component name misspelled

C. Port map uses positional mapping incorrectly

D. Missing port mapping for output 'count'

Solution

1. Step 1: Check component ports and instantiation

   Component Counter has two ports: clk (input) and count (output).

2. Step 2: Verify port map completeness

   Instantiation maps clk but misses mapping for output count, which is required.

3. Final Answer:

   Missing port mapping for output 'count' -> Option D

4. Quick Check:

   All ports must be mapped [OK]

Hint: Map all ports in component instantiation [OK]

Common Mistakes:

• Ignoring output port mapping
• Assuming partial port map is allowed
• Confusing port names or signals

5. You have a top-level design that instantiates two components: ALU and RegisterFile. To follow best practices in design hierarchy, which approach is recommended?

hard

A. Use global signals for all internal connections without ports

B. Declare components in the architecture and instantiate them with clear labels and port maps

C. Write all logic inside the top-level architecture without components

D. Instantiate components without declaring them first

Solution

1. Step 1: Understand best practices for hierarchy

   Best practice is to declare components explicitly and instantiate them with labels and port maps for clarity and modularity.

2. Step 2: Evaluate other options

   Writing all logic in one place reduces modularity; global signals break encapsulation; instantiating undeclared components causes errors.

3. Final Answer:

   Declare components in the architecture and instantiate them with clear labels and port maps -> Option B

4. Quick Check:

   Clear declaration + instantiation = best practice [OK]

Hint: Declare then instantiate components clearly [OK]

Common Mistakes:

• Skipping component declarations
• Using global signals instead of ports
• Putting all logic in one big block