Configuration declaration in VHDL - Mini Project: Build & Apply

VHDL Configuration Declaration

📖 Scenario: You are designing a simple digital system in VHDL. You want to control which architecture of a component is used in your design by using a configuration declaration.

🎯 Goal: Build a VHDL configuration declaration that selects a specific architecture for a component in your design.

📋 What You'll Learn

Create an entity and two architectures for a component

Declare a configuration that binds the component to one architecture

Use the configuration in a top-level design

Print the selected architecture name as a comment

💡 Why This Matters

🌍 Real World

In real digital design projects, configuration declarations help select specific implementations of components without changing the top-level code.

💼 Career

Understanding configuration declarations is important for FPGA and ASIC designers who need flexible and reusable VHDL code.

1

Create the component entity and two architectures

Write a VHDL entity called MyComponent with a single input clk and output out_sig. Then write two architectures named arch_a and arch_b for MyComponent. Each architecture should assign a different constant value to out_sig.

VHDL

-- Write the entity MyComponent and two architectures arch_a and arch_b
-- Your code here

Hint

Define the entity with ports first. Then create two architectures with different output assignments.

2

Declare a configuration to select architecture arch_b

Write a VHDL configuration called MyComponent_cfg for MyComponent that binds the component to the architecture arch_b.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MyComponent is
    Port ( clk : in STD_LOGIC;
           out_sig : out STD_LOGIC);
end MyComponent;

architecture arch_a of MyComponent is
begin
    out_sig <= '0';
end arch_a;

architecture arch_b of MyComponent is
begin
    out_sig <= '1';
end arch_b;

-- Declare configuration MyComponent_cfg to bind arch_b
-- Your code here

Hint

Use the configuration keyword and specify the architecture name after for.

3

Create a top-level entity that uses MyComponent

Write a VHDL entity called TopLevel with input clk and output top_out. Instantiate MyComponent inside TopLevel and connect ports accordingly.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MyComponent is
    Port ( clk : in STD_LOGIC;
           out_sig : out STD_LOGIC);
end MyComponent;

architecture arch_a of MyComponent is
begin
    out_sig <= '0';
end arch_a;

architecture arch_b of MyComponent is
begin
    out_sig <= '1';
end arch_b;

configuration MyComponent_cfg of MyComponent is
    for arch_b
    end for;
end MyComponent_cfg;

entity TopLevel is
    Port ( clk : in STD_LOGIC;
           top_out : out STD_LOGIC);
end TopLevel;

architecture rtl of TopLevel is
    component MyComponent
        Port ( clk : in STD_LOGIC;
               out_sig : out STD_LOGIC);
    end component;

    signal internal_sig : STD_LOGIC;
begin
    -- Instantiate MyComponent here
    -- Your code here

Hint

Declare the component inside the architecture, create a signal, and instantiate the component with port map.

4

Use the configuration in the top-level design and output the selected architecture

Add a configuration declaration called TopLevel_cfg for TopLevel that uses MyComponent_cfg to bind the component. Then write a comment showing the selected architecture name arch_b.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MyComponent is
    Port ( clk : in STD_LOGIC;
           out_sig : out STD_LOGIC);
end MyComponent;

architecture arch_a of MyComponent is
begin
    out_sig  clk, out_sig => internal_sig);
    top_out <= internal_sig;
end rtl;

-- Declare configuration TopLevel_cfg to use MyComponent_cfg
-- Add a comment showing the selected architecture arch_b
-- Your code here

Hint

Use nested for statements in the configuration to bind the component configuration.

Practice

1. What is the main purpose of a configuration declaration in VHDL?

easy

A. To specify timing constraints for simulation

B. To declare signals inside an architecture

C. To define new data types

D. To select which architecture is used for a component instance

Solution

1. Step 1: Understand the role of configuration declarations

   Configuration declarations in VHDL are used to specify which architecture should be bound to a component instance.

2. Step 2: Compare with other options

   Declaring signals, defining data types, or specifying timing constraints are done elsewhere, not in configurations.

3. Final Answer:

   To select which architecture is used for a component instance -> Option D

4. Quick Check:

   Configuration = Architecture selection [OK]

Hint: Configurations pick architectures for components quickly [OK]

Common Mistakes:

• Confusing configuration with signal declaration
• Thinking configuration defines data types
• Assuming configuration sets timing constraints

2. Which of the following is the correct syntax to start a configuration declaration in VHDL?

easy

A. configuration ConfigName for EntityName is

B. config ConfigName for EntityName begin

C. config ConfigName of EntityName begin

D. configuration ConfigName of EntityName is

Solution

1. Step 1: Recall VHDL configuration syntax

   The correct syntax starts with the keyword configuration, followed by the configuration name, then for, then the entity name, and ends with is.

2. Step 2: Match options with correct syntax

   configuration ConfigName for EntityName is matches exactly: configuration ConfigName for EntityName is. Others use incorrect keywords or order.

3. Final Answer:

   configuration ConfigName for EntityName is -> Option A

4. Quick Check:

   Syntax = configuration ... for ... is [OK]

Hint: Use 'configuration Name for Entity is' to start [OK]

Common Mistakes:

• Using 'of' instead of 'for'
• Omitting 'is' keyword
• Using 'config' instead of 'configuration'

3. Given the following VHDL configuration snippet:

configuration CFG1 for MyEntity is
  for ARCH1
    for U1: MyComponent
      use entity work.MyComponent(ARCH2);
    end for;
  end for;
end CFG1;

What architecture is used for the component instance U1 inside MyEntity when CFG1 is applied?

medium

A. ARCH1

B. MyEntity

C. ARCH2

D. work.MyComponent

Solution

1. Step 1: Analyze the configuration binding

   The configuration CFG1 binds the architecture ARCH1 to MyEntity. Inside ARCH1, the component instance U1 is explicitly bound to the architecture ARCH2 of MyComponent.

2. Step 2: Identify the architecture used for U1

   Because of the line use entity work.MyComponent(ARCH2);, U1 uses ARCH2, not ARCH1 or the entity name.

3. Final Answer:

   ARCH2 -> Option C

4. Quick Check:

   Instance U1 uses ARCH2 architecture [OK]

Hint: Look for 'use entity ... (ARCH)' inside configuration [OK]

Common Mistakes:

• Assuming U1 uses ARCH1 because of outer for
• Confusing entity name with architecture
• Ignoring nested 'use entity' clause

4. Identify the error in this VHDL configuration declaration:

configuration CFG2 for MyEntity is
  for ARCH1
    for U1: MyComponent
      use entity work.MyComponent(ARCH2)
    end for;
  end for;
end CFG2;

medium

A. Wrong keyword 'for' instead of 'of' in configuration header

B. Missing semicolon after 'use entity' statement

C. Component instance name 'U1' is invalid

D. Entity name 'MyEntity' is missing

Solution

1. Step 1: Check syntax of 'use entity' statement

   In VHDL configurations, each statement must end with a semicolon. The line use entity work.MyComponent(ARCH2) is missing a semicolon.

2. Step 2: Verify other parts

   The configuration header uses correct keywords, the instance name U1 is valid, and the entity name MyEntity is present.

3. Final Answer:

   Missing semicolon after 'use entity' statement -> Option B

4. Quick Check:

   Statements end with semicolon [OK]

Hint: Check semicolons after each statement in configuration [OK]

Common Mistakes:

• Omitting semicolon after 'use entity' line
• Confusing 'for' and 'of' keywords
• Assuming instance names must be uppercase

5. You have two architectures for an entity Processor: FastArch and SafeArch. You want to create a configuration that uses FastArch by default but switches to SafeArch for the component instance ALU inside Processor. Which configuration declaration correctly implements this?

hard

A. configuration CFG for Processor is
for FastArch
for ALU: ALUComponent
use entity work.ALUComponent(SafeArch);
end for;
end for;
end CFG;

B. configuration CFG for Processor is
for FastArch
for ALU: ALUComponent
use entity work.Processor(SafeArch);
end for;
end for;
end CFG;

C. configuration CFG for Processor is
for SafeArch
for ALU: ALUComponent
use entity work.ALUComponent(FastArch);
end for;
end for;
end CFG;

D. configuration CFG for Processor is
for FastArch
for ALU: Processor
use entity work.ALUComponent(SafeArch);
end for;
end for;
end CFG;

Solution

1. Step 1: Understand the requirement

   The configuration should use FastArch for Processor by default, but for the component instance ALU of type ALUComponent, it should use SafeArch.

2. Step 2: Check each option

   configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.ALUComponent(SafeArch); end for; end for; end CFG; correctly binds FastArch to Processor and overrides ALU instance to use SafeArch architecture of ALUComponent. configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.Processor(SafeArch); end for; end for; end CFG; incorrectly tries to bind SafeArch to Processor entity instead of ALUComponent. configuration CFG for Processor is for SafeArch for ALU: ALUComponent use entity work.ALUComponent(FastArch); end for; end for; end CFG; reverses the default and override. configuration CFG for Processor is for FastArch for ALU: Processor use entity work.ALUComponent(SafeArch); end for; end for; end CFG; incorrectly uses ALU instance as Processor type.

3. Final Answer:

   configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.ALUComponent(SafeArch); end for; end for; end CFG; -> Option A

4. Quick Check:

   Default architecture + instance override = configuration CFG for Processor is for FastArch for ALU: ALUComponent use entity work.ALUComponent(SafeArch); end for; end for; end CFG; [OK]

Hint: Override instance architecture with 'use entity work.Component(Arch)' [OK]

Common Mistakes:

• Binding wrong entity in 'use entity' clause
• Swapping default and override architectures
• Using instance name as entity type