Clock divider with enable in VHDL - Mini Project: Build & Apply

Clock divider with enable

📖 Scenario: You are designing a digital circuit that needs a slower clock signal derived from a faster input clock. This is common in electronics when different parts of a system run at different speeds. You will create a clock divider that only counts and toggles the output clock when an enable signal is active.

🎯 Goal: Build a VHDL module that divides the input clock frequency by 4, but only when an enable signal is high. When enable is low, the output clock should not toggle.

📋 What You'll Learn

Create a signal to count clock cycles.

Add an enable input signal to control counting.

Toggle the output clock every 2 counts when enabled.

Output clock should not change when enable is low.

💡 Why This Matters

🌍 Real World

Clock dividers are used in digital electronics to generate slower clocks from a fast master clock, useful for timing control in microcontrollers, communication devices, and other digital circuits.

💼 Career

Understanding clock dividers and enable signals is important for hardware engineers and FPGA developers who design synchronous digital systems.

1

Create the clock divider entity and signals

Write a VHDL entity named clock_divider with inputs clk and enable of type std_logic, and output clk_out of type std_logic. Inside the architecture, declare a signal count of type integer range 0 to 3 initialized to 0, and a signal clk_out of type std_logic initialized to '0'.

VHDL

-- Write the entity and architecture header
-- Declare signals count and clk_out

Hint

Remember to declare the entity with the correct ports and inside the architecture declare the signals with initial values.

2

Add a process triggered by the rising edge of clk

Inside the architecture, add a process sensitive to clk. Use if rising_edge(clk) to detect clock edges. Inside the process, check if enable = '1' to allow counting. If enabled, increment count by 1 and reset it to 0 when it reaches 4.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_divider is
    port(
        clk : in std_logic;
        enable : in std_logic;
        clk_out : out std_logic
    );
end entity clock_divider;

architecture Behavioral of clock_divider is
    signal count : integer range 0 to 3 := 0;
    signal clk_out_reg : std_logic := '0';
begin
    clk_out <= clk_out_reg;

    process(clk)
    begin
        if rising_edge(clk) then
            -- Add enable check and count increment here
        end if;
    end process;
end Behavioral;

Hint

Use a process triggered by clk. Inside, check for rising edge and enable signal before updating count.

3

Toggle output clock every 2 counts when enabled

Inside the same process, after updating count, toggle clk_out_reg when count equals 1 or 3. This will divide the clock frequency by 4 when enabled.

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_divider is
    port(
        clk : in std_logic;
        enable : in std_logic;
        clk_out : out std_logic
    );
end entity clock_divider;

architecture Behavioral of clock_divider is
    signal count : integer range 0 to 3 := 0;
    signal clk_out_reg : std_logic := '0';
begin
    clk_out <= clk_out_reg;

    process(clk)
    begin
        if rising_edge(clk) then
            if enable = '1' then
                if count = 3 then
                    count <= 0;
                else
                    count <= count + 1;
                end if;
                if count = 1 or count = 3 then
                    -- Toggle clk_out_reg here
                end if;
            end if;
        end if;
    end process;
end Behavioral;

Hint

Toggle the output clock signal by assigning clk_out_reg <= not clk_out_reg when count is 1 or 3.

4

Test output clock does not toggle when enable is low

Add an else branch after if enable = '1' inside the process to keep clk_out_reg unchanged when enable = '0'. Then add a report statement outside the process to print "Clock divider with enable ready".

VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_divider is
    port(
        clk : in std_logic;
        enable : in std_logic;
        clk_out : out std_logic
    );
end entity clock_divider;

architecture Behavioral of clock_divider is
    signal count : integer range 0 to 3 := 0;
    signal clk_out_reg : std_logic := '0';
begin
    clk_out <= clk_out_reg;

    process(clk)
    begin
        if rising_edge(clk) then
            if enable = '1' then
                if count = 3 then
                    count <= 0;
                else
                    count <= count + 1;
                end if;
                if count = 1 or count = 3 then
                    clk_out_reg <= not clk_out_reg;
                end if;
            else
                -- Keep clk_out_reg unchanged when enable is '0'
            end if;
        end if;
    end process;

    -- Add a report statement here
end Behavioral;

Hint

Use an else branch to keep clk_out_reg unchanged when enable is low. Add a report statement to confirm the design is ready.

Practice

1. What is the main purpose of a clock divider with enable in VHDL?

easy

A. To reset the clock signal automatically

B. To increase the clock frequency permanently

C. To generate a random clock signal

D. To slow down the clock signal only when the enable is active

Solution

1. Step 1: Understand clock divider function

   A clock divider reduces the frequency of the input clock signal.

2. Step 2: Role of enable signal

   The enable signal controls when the clock divider is active, so it only slows the clock when enabled.

3. Final Answer:

   To slow down the clock signal only when the enable is active -> Option D

4. Quick Check:

   Clock divider + enable = slow clock only if enabled [OK]

Hint: Enable controls when clock slows down [OK]

Common Mistakes:

• Thinking clock always slows down regardless of enable
• Confusing enable with reset
• Assuming clock frequency increases

2. Which of the following is the correct VHDL syntax to declare an enable input signal in an entity?

easy

A. enable : in std_logic;

B. enable : out std_logic;

C. enable : in integer;

D. enable : buffer std_logic;

Solution

1. Step 1: Identify signal direction for enable

   Enable is an input signal, so direction must be 'in'.

2. Step 2: Identify signal type for enable

   Enable is usually a single bit signal, so type is 'std_logic'.

3. Final Answer:

   enable : in std_logic; -> Option A

4. Quick Check:

   Enable input signal = in std_logic [OK]

Hint: Enable is input, so use 'in std_logic' [OK]

Common Mistakes:

• Using 'out' instead of 'in' for enable
• Using integer type for enable
• Using 'buffer' incorrectly

3. Given this VHDL process snippet for a clock divider with enable:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    clk_out <= '0';
  elsif rising_edge(clk) then
    if enable = '1' then
      if count = 3 then
        clk_out <= not clk_out;
        count <= 0;
      else
        count <= count + 1;
      end if;
    end if;
  end if;
end process;

What is the frequency division factor of clk_out relative to clk when enabled?

medium

A. 4

B. 2

C. 8

D. 3

Solution

1. Step 1: Understand counting and toggling

   The counter counts from 0 to 3 (4 counts). When count=3, clk_out toggles.

2. Step 2: Calculate division factor

   Each toggle happens every 4 clock cycles, so full clk_out period is 8 clk cycles (toggle twice for full cycle).

3. Final Answer:

   8 -> Option C

4. Quick Check:

   Toggle every 4 cycles -> divide by 8 frequency [OK]

Hint: Toggle output every 4 cycles means divide by 8 [OK]

Common Mistakes:

• Confusing toggle count with division factor
• Counting only half the period
• Ignoring enable condition

4. Identify the error in this VHDL clock divider process with enable:

process(clk, reset)
begin
  if reset = '1' then
    count <= 0;
    clk_out <= '0';
  elsif rising_edge(clk) then
    if enable = '1' then
      if count = 4 then
        clk_out <= not clk_out;
        count <= 0;
      else
        count <= count + 1;
      end if;
    end if;
  end if;
end process;

What is the main problem?

medium

A. Missing else clause for enable = '0'

B. Counter compares to 4 but counts from 0, causing off-by-one error

C. clk_out toggles on falling edge instead of rising edge

D. Reset condition is inside rising_edge(clk) block

Solution

1. Step 1: Check counter comparison

   Counter counts from 0 upwards, but compares to 4, so counts 0 to 4 (5 counts).

2. Step 2: Identify off-by-one error

   Usually counter should compare to max count minus 1 (3 for 4 counts), so this causes timing error.

3. Final Answer:

   Counter compares to 4 but counts from 0, causing off-by-one error -> Option B

4. Quick Check:

   Count 0 to 4 means 5 counts, off-by-one [OK]

Hint: Count from 0 means max compare is count-1 [OK]

Common Mistakes:

• Thinking enable needs else clause
• Confusing reset placement
• Misreading edge sensitivity

5. You want to design a clock divider with enable that divides the input clock by 10 only when enabled. Which approach correctly implements this in VHDL?

hard

A. Use a 5-bit counter counting 0 to 4, toggle output on count=4, increment counter only if enable='1'

B. Use a 3-bit counter counting 0 to 4, toggle output on count=4, ignore enable signal

C. Use a 4-bit counter counting 0 to 10, toggle output on count=10, reset counter on reset only

D. Use a 4-bit counter counting 0 to 9, toggle output on count=9, reset counter on enable='0'

Solution

1. Step 1: Determine counter size and range

   Dividing by 10 requires counting 5 clock cycles (0 to 4), so 3 bits are enough but 5 bits also work safely.

2. Step 2: Control counter with enable

   Counter should increment only when enable='1' to slow clock only when enabled.

3. Step 3: Toggle output on max count

   Toggle output clock when count reaches 4, then reset counter to 0.

4. Final Answer:

   Use a 5-bit counter counting 0 to 4, toggle output on count=4, increment counter only if enable='1' -> Option A

5. Quick Check:

   Count 0-4 + enable control = correct divider [OK]

Hint: Increment counter only when enabled for correct division [OK]

Common Mistakes:

• Ignoring enable signal in counter increment
• Counting wrong range causing wrong division
• Resetting counter on enable='0' instead of pause