Why FSMs control complex sequential behavior in VHDL - Test Your Understanding

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a state type in VHDL.

VHDL

type state_type is ([1]);

Drag options to blanks, or click blank then click option'

AIDLE, RUNNING, STOPPED

Bstart, stop

CIDLE

Dstate1, state2

Attempts:

3 left

💡 Hint

Common Mistakes

Including multiple states without commas or parentheses.

Using lowercase state names without quotes.

In VHDL, when declaring an enumeration type, the states are listed inside parentheses separated by commas. Here, only one state 'IDLE' is declared as a simple example.

2fill in blank

medium

Complete the code to define the next state logic in a process.

VHDL

process(current_state, input_signal) begin
  case current_state is
    when IDLE =>
      if input_signal = '1' then
        next_state <= [1];
      else
        next_state <= IDLE;
      end if;
    when others =>
      next_state <= IDLE;
  end case;
end process;

Drag options to blanks, or click blank then click option'

ARUNNING

BSTOPPED

CIDLE

DSTART

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning next_state to IDLE again, causing no state change.

Using a state name not declared in the type.

When the FSM is in IDLE and input_signal is '1', the next state should be RUNNING to start the operation.

3fill in blank

hard

Fix the error in the state register process to update the current state on clock edge.

VHDL

process(clk, reset) begin
  if reset = '1' then
    current_state <= IDLE;
  elsif rising_edge([1]) then
    current_state <= next_state;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Areset

Bclk

Cnext_state

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using reset or other signals in rising_edge instead of clk.

Forgetting to use rising_edge function.

The state register updates on the rising edge of the clock signal 'clk', not on reset or other signals.

4fill in blank

hard

Fill both blanks to complete the output logic based on the current state.

VHDL

process(current_state) begin
  case current_state is
    when IDLE => output_signal <= [1];
    when RUNNING => output_signal <= [2];
    when others => output_signal <= '0';
  end case;
end process;

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A'0'

B'1'

C'Z'

D'X'

Attempts:

3 left

💡 Hint

Common Mistakes

Using '1' in IDLE state causing output to be on when idle.

Using undefined signal values like 'Z' or 'X'.

In IDLE state, output_signal is '0' (off). In RUNNING state, output_signal is '1' (on).

5fill in blank

hard

Fill all three blanks to complete the FSM state transition with an additional STOPPED state.

VHDL

type state_type is (IDLE, RUNNING, [1]);

process(current_state, input_signal) begin
  case current_state is
    when IDLE =>
      if input_signal = '1' then
        next_state <= RUNNING;
      else
        next_state <= IDLE;
      end if;
    when RUNNING =>
      if input_signal = '0' then
        next_state <= [2];
      else
        next_state <= RUNNING;
      end if;
    when [3] =>
      next_state <= IDLE;
    when others =>
      next_state <= IDLE;
  end case;
end process;

Drag options to blanks, or click blank then click option'

ASTOPPED

BPAUSED

DHALT

Attempts:

3 left

💡 Hint

Common Mistakes

Using inconsistent state names in different parts of the code.

Forgetting to include the new state in the type declaration.

The additional state is STOPPED. The FSM moves to STOPPED from RUNNING when input_signal is '0', and from STOPPED it returns to IDLE.

Practice

1. Why are FSMs (Finite State Machines) used to control complex sequential behavior in VHDL designs?

easy

A. Because they organize behavior into clear, manageable states.

B. Because they make the circuit run faster than combinational logic.

C. Because they eliminate the need for clocks in the design.

D. Because they reduce the number of input signals required.

Solution

1. Step 1: Understand FSM purpose

   FSMs break down complex sequences into smaller states, making behavior easier to manage.

2. Step 2: Compare to other options

   FSMs do not inherently speed circuits, remove clocks, or reduce inputs; their main role is organizing states.

3. Final Answer:

   Because they organize behavior into clear, manageable states. -> Option A

4. Quick Check:

   FSMs = clear state management [OK]

Hint: FSMs split tasks into states for easy control [OK]

Common Mistakes:

• Thinking FSMs make circuits faster
• Believing FSMs remove clock signals
• Assuming FSMs reduce input count

2. Which VHDL code snippet correctly declares a simple FSM state type?

easy

A. type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type;

B. signal state : integer range 0 to 2;\ntype state_type is (IDLE, PROCESS, DONE);

C. type state_type is array (0 to 2) of std_logic;\nsignal state : state_type;

D. signal state : std_logic_vector(1 downto 0);\ntype state_type is (IDLE, PROCESS, DONE);

Solution

1. Step 1: Identify correct state type declaration

   type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type; correctly defines an enumerated type with states and a signal of that type.

2. Step 2: Check other options

   signal state : integer range 0 to 2;\ntype state_type is (IDLE, PROCESS, DONE); declares signal before type, which is invalid. type state_type is array (0 to 2) of std_logic;\nsignal state : state_type; uses array instead of enumeration. signal state : std_logic_vector(1 downto 0);\ntype state_type is (IDLE, PROCESS, DONE); mixes vector with enumeration incorrectly.

3. Final Answer:

   type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type; -> Option A

4. Quick Check:

   Correct enum type declaration = type state_type is (IDLE, PROCESS, DONE);\nsignal state : state_type; [OK]

Hint: Declare enum type before signal using it [OK]

Common Mistakes:

• Declaring signal before type
• Using arrays instead of enums for states
• Mixing std_logic_vector with enum states

3. Given the following VHDL FSM snippet, what is the next state when current state is PROCESS and input start = '0'?

type state_type is (IDLE, PROCESS, DONE);
signal state : state_type;

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if start = '1' then
          state <= PROCESS;
        else
          state <= IDLE;
        end if;
      when PROCESS =>
        if start = '0' then
          state <= DONE;
        else
          state <= PROCESS;
        end if;
      when DONE =>
        state <= IDLE;
    end case;
  end if;
end process;

medium

A. IDLE

B. PROCESS

C. DONE

D. ERROR

Solution

1. Step 1: Analyze current state and input

   Current state is PROCESS and input start = '0'. According to code, PROCESS state moves to DONE if start = '0'.

2. Step 2: Determine next state

   Since start = '0', next state is DONE.

3. Final Answer:

   DONE -> Option C

4. Quick Check:

   PROCESS + start='0' = DONE [OK]

Hint: Follow case conditions for current state and input [OK]

Common Mistakes:

• Ignoring input value in state transition
• Confusing PROCESS and DONE states
• Assuming default next state is IDLE

4. Identify the error in this FSM process code snippet:

process(clk)
begin
  if clk'event and clk = '1' then
    case state is
      when IDLE =>
        if start = '1' then
          state <= PROCESS;
        end if;
      when PROCESS =>
        state <= DONE;
      when DONE =>
        state <= IDLE;
    end case;
  end if;
end process;

medium

A. Missing else branch in IDLE state causes latch inference.

B. Using clk'event instead of rising_edge(clk) is incorrect.

C. State transitions are not inside a clocked process.

D. No reset condition to initialize the state signal.

Solution

1. Step 1: Check clock event usage

   Using clk'event and clk = '1' is valid but less recommended than rising_edge(clk), so not an error.

2. Step 2: Look for reset signal

   The code lacks any reset condition to initialize the state signal, which can cause undefined behavior.

3. Final Answer:

   No reset condition to initialize the state signal. -> Option D

4. Quick Check:

   Missing reset = No reset condition to initialize the state signal. [OK]

Hint: Always include reset to set initial FSM state [OK]

Common Mistakes:

• Confusing clk'event with rising_edge(clk)
• Assuming else needed in every if
• Ignoring reset importance

5. You want to design an FSM in VHDL that controls a traffic light sequence: RED -> GREEN -> YELLOW -> RED. Which approach best uses FSMs to handle this complex sequential behavior?

hard

A. Use combinational logic only to switch lights based on input sensors.

B. Define states RED, GREEN, YELLOW and transition on a timer signal in a clocked process.

C. Use multiple independent signals toggling asynchronously for each light.

D. Write separate processes for each light color without state tracking.

Solution

1. Step 1: Identify FSM role in traffic light control

   FSMs manage sequences by defining states and transitions, perfect for timed traffic light changes.

2. Step 2: Evaluate options

   Define states RED, GREEN, YELLOW and transition on a timer signal in a clocked process. uses states and timer in a clocked process, matching FSM design principles. Others lack clear state control or timing.

3. Final Answer:

   Define states RED, GREEN, YELLOW and transition on a timer signal in a clocked process. -> Option B

4. Quick Check:

   FSM + timer = controlled traffic light sequence [OK]

Hint: Use states and timer in clocked process for sequences [OK]

Common Mistakes:

• Using only combinational logic for sequence
• Toggling signals asynchronously causing glitches
• Not tracking state leads to unpredictable behavior