Vending machine FSM example in VHDL - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of Vending Machine FSM after inserting coins

Consider a VHDL vending machine FSM that accepts 5-cent and 10-cent coins to reach a total of 15 cents to dispense an item. What is the output signal dispense after the input sequence: insert 10 cents, then 5 cents?

VHDL

library ieee;
use ieee.std_logic_1164.all;

entity vending_machine is
  port(
    clk      : in std_logic;
    reset    : in std_logic;
    coin_5   : in std_logic;
    coin_10  : in std_logic;
    dispense : out std_logic
  );
end vending_machine;

architecture fsm of vending_machine is
  type state_type is (S0, S5, S10, S15);
  signal state, next_state : state_type;
begin
  process(clk, reset) is
  begin
    if reset = '1' then
      state <= S0;
    elsif rising_edge(clk) then
      state <= next_state;
    end if;
  end process;

  process(state, coin_5, coin_10) is
  begin
    dispense <= '0';
    case state is
      when S0 =>
        if coin_5 = '1' then
          next_state <= S5;
        elsif coin_10 = '1' then
          next_state <= S10;
        else
          next_state <= S0;
        end if;
      when S5 =>
        if coin_5 = '1' then
          next_state <= S10;
        elsif coin_10 = '1' then
          next_state <= S15;
        else
          next_state <= S5;
        end if;
      when S10 =>
        if coin_5 = '1' then
          next_state <= S15;
        elsif coin_10 = '1' then
          next_state <= S15; -- Overpay treated as 15
        else
          next_state <= S10;
        end if;
      when S15 =>
        dispense <= '1';
        next_state <= S0;
      when others =>
        next_state <= S0;
    end case;
  end process;
end fsm;

A dispense never becomes '1'

B dispense = '0' after second coin

C dispense = '1' after first coin

D dispense = '1' after second coin

💡 Hint

Think about the total value after inserting 10 cents then 5 cents.

The FSM moves from S0 to S10 after the first 10-cent coin, then from S10 to S15 after the 5-cent coin. At S15, dispense is set to '1'.

🧠 Conceptual

intermediate

Number of states in the vending machine FSM

How many states are needed in a vending machine FSM that accepts 5-cent and 10-cent coins to dispense an item costing 15 cents?

A 4 states

B 3 states

C 5 states

D 6 states

💡 Hint

Count all possible sums of inserted coins up to 15 cents.

States represent sums: 0, 5, 10, and 15 cents, so 4 states are needed.

🔧 Debug

advanced

Identify the error in this VHDL vending machine FSM snippet

What error will this VHDL code cause? process(state, coin_5, coin_10) is begin dispense <= '0'; case state is when S0 => if coin_5 = '1' then next_state <= S5 elsif coin_10 = '1' then next_state <= S10; else next_state <= S0; end if; when others => next_state <= S0; end case; end process;

A Runtime error: next_state not assigned in all branches

B Syntax error: missing semicolon after next_state <= S5

C Logic error: dispense signal never set to '1'

D No error, code runs fine

💡 Hint

Check each statement for proper VHDL syntax.

The line 'next_state <= S5' is missing a semicolon, causing a syntax error.

📝 Syntax

advanced

Correct way to reset FSM state in VHDL

Which code snippet correctly resets the FSM state to S0 on reset signal in VHDL?

A

if rising_edge(clk) then
  if reset = '1' then
    state <= S0;
  else
    state <= next_state;
  end if;
end if;

B

if reset = '1' then
  state <= S0;
elsif rising_edge(clk) then
  state <= next_state;
end if;

C

if reset = '1' then
  next_state <= S0;
elsif rising_edge(clk) then
  state <= next_state;
end if;

D

if rising_edge(clk) then
  state <= next_state;
elsif reset = '1' then
  state <= S0;
end if;

💡 Hint

Reset should be checked inside the clock edge condition for synchronous reset.

Option A shows a synchronous reset inside the rising edge clock check, which is correct.

🚀 Application

expert

Calculate total dispense signals in a coin sequence

Given the vending machine FSM from the example, if the input coin sequence over 6 clock cycles is: 5c, 5c, 10c, 5c, 10c, 5c (one coin per cycle), how many times will the dispense signal be '1'?

A 2 times

B 4 times

C 3 times

D 5 times

💡 Hint

Track the state transitions and when the total reaches or exceeds 15 cents.

The FSM dispenses when reaching 15 cents. The sequence causes dispense at cycles 3, 5, and 6.

Practice

1. What is the main purpose of a vending machine FSM in VHDL?

easy

A. To perform complex mathematical calculations

B. To control the sequence of accepting coins and dispensing items

C. To store large amounts of data permanently

D. To display graphics on a screen

Solution

1. Step 1: Understand FSM role in vending machine

   The FSM (Finite State Machine) controls the order of operations like accepting coins and dispensing items.

2. Step 2: Compare options to FSM purpose

   Only To control the sequence of accepting coins and dispensing items describes controlling the sequence of actions, which matches FSM's role.

3. Final Answer:

   To control the sequence of accepting coins and dispensing items -> Option B

4. Quick Check:

   FSM controls sequence = To control the sequence of accepting coins and dispensing items [OK]

Hint: FSM controls steps in process flow, not data storage or math [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM does math or graphics
• Ignoring the sequence control aspect

2. Which VHDL statement correctly declares a state type for a vending machine FSM?

easy

A. signal state : integer := 0;

B. variable state : std_logic_vector(1 downto 0);

C. type state_type is (IDLE, COIN_INSERTED, DISPENSE);

D. constant state : boolean := true;

Solution

1. Step 1: Identify correct state type declaration

   States in FSM are usually declared as an enumerated type listing all states.

2. Step 2: Check options for enumerated type

   type state_type is (IDLE, COIN_INSERTED, DISPENSE); declares a type with named states, which is correct for FSM states.

3. Final Answer:

   type state_type is (IDLE, COIN_INSERTED, DISPENSE); -> Option C

4. Quick Check:

   State type enum = type state_type is (IDLE, COIN_INSERTED, DISPENSE); [OK]

Hint: FSM states use enumerated types, not integers or booleans [OK]

Common Mistakes:

• Using integer or boolean instead of enumerated type
• Confusing signal and type declarations
• Using variable instead of type for states

3. Given this VHDL snippet inside a vending machine FSM process:

case state is
  when IDLE =>
    if coin = '1' then
      next_state <= COIN_INSERTED;
    else
      next_state <= IDLE;
    end if;
  when COIN_INSERTED =>
    next_state <= DISPENSE;
  when DISPENSE =>
    next_state <= IDLE;
end case;

What will be the next state if current state is IDLE and coin = '0'?

medium

A. COIN_INSERTED

B. Undefined

C. DISPENSE

D. IDLE

Solution

1. Step 1: Analyze the IDLE state condition

   If coin = '1', next_state is COIN_INSERTED; else next_state remains IDLE.

2. Step 2: Apply coin = '0' condition

   Since coin = '0', the else branch applies, so next_state stays IDLE.

3. Final Answer:

   IDLE -> Option D

4. Quick Check:

   coin '0' in IDLE = next_state IDLE [OK]

Hint: Check coin input condition in IDLE state carefully [OK]

Common Mistakes:

• Assuming coin '0' moves to COIN_INSERTED
• Confusing next_state with current state
• Ignoring else branch in if statement

4. Identify the error in this VHDL FSM process snippet for a vending machine:

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when IDLE =>
        if coin = '1' then
          state <= COIN_INSERTED;
        end if;
      when COIN_INSERTED =>
        state <= DISPENSE;
      when DISPENSE =>
        state <= IDLE;
    end case;
  end if;
end process;

medium

A. No reset condition for state initialization

B. State variable should be a signal, not variable

C. No default case in case statement

D. Missing else branch in IDLE state causes latch

Solution

1. Step 1: Check for reset condition in FSM process

   FSM processes usually include a reset to initialize the state at start.

2. Step 2: Identify missing reset

   This code lacks any reset signal or condition to set initial state, which is an error.

3. Final Answer:

   No reset condition for state initialization -> Option A

4. Quick Check:

   Missing reset = No reset condition for state initialization [OK]

Hint: Always include reset to set initial FSM state [OK]

Common Mistakes:

• Thinking else branch missing causes latch in synchronous process
• Confusing signal and variable usage
• Ignoring importance of reset in FSM

5. You want to extend a vending machine FSM to accept two coin types: 5 cents and 10 cents. The FSM should dispense an item when total inserted coins reach 15 cents or more. Which approach correctly updates the FSM to handle this?

hard

A. Add a coin_value input and a coin_total signal; update coin_total on each coin and transition to DISPENSE when coin_total >= 15

B. Use two separate FSMs for 5 and 10 cent coins and combine outputs

C. Ignore coin values and dispense after 3 coins inserted

D. Add a timer to dispense item after fixed time regardless of coins

Solution

1. Step 1: Understand requirement to track coin values

   We must track total coin value inserted, not just count coins.

2. Step 2: Choose approach to accumulate coin values

   Add a coin_value input and a coin_total signal; update coin_total on each coin and transition to DISPENSE when coin_total >= 15 uses a coin_value input and coin_total signal to sum coins and trigger dispense when total >= 15, which fits requirement.

3. Final Answer:

   Add a coin_value input and a coin_total signal; update coin_total on each coin and transition to DISPENSE when coin_total >= 15 -> Option A

4. Quick Check:

   Track coin values and total = Add coin_value and coin_total, dispense at 15+ [OK]

Hint: Sum coin values, dispense when total reaches target [OK]

Common Mistakes:

• Using separate FSMs instead of one with coin total
• Counting coins instead of summing values
• Dispensing by time, not coin total