Two-process FSM coding style in VHDL - Step-by-Step Execution

Concept Flow - Two-process FSM coding style

Clock Edge Detected

↓

Update State Register

↓

Evaluate Next State Logic

↓

Evaluate Output Logic

↓

Wait for Next Clock Edge

The two-process FSM style separates state updating on clock edges from next state and output logic evaluation, improving clarity and synthesis.

Execution Sample

VHDL

process(clk, reset)
begin
  if reset = '1' then
    state <= IDLE;
  elsif rising_edge(clk) then
    state <= next_state;
  end if;
end process;

process(state, input_signal)
begin
  case state is
    when IDLE =>
      if input_signal = '1' then
        next_state <= BUSY;
      else
        next_state <= IDLE;
      end if;
    when BUSY =>
      next_state <= IDLE;
    when others =>
      next_state <= IDLE;
  end case;
end process;

This VHDL code shows a two-process FSM: one process updates the state on clock edges, the other computes next state based on current state and inputs.

Execution Table

Step	clk	reset	state (before)	input_signal	next_state (computed)	state (after)
1	0	1	X (unknown)	0	IDLE	IDLE
2	1 (rising)	0	IDLE	0	IDLE	IDLE
3	0	0	IDLE	1	BUSY	IDLE
4	1 (rising)	0	IDLE	1	BUSY	BUSY
5	0	0	BUSY	0	IDLE	BUSY
6	1 (rising)	0	BUSY	0	IDLE	IDLE
7	0	0	IDLE	0	IDLE	IDLE
8	1 (rising)	0	IDLE	0	IDLE	IDLE

💡 Simulation ends after several clock cycles showing state transitions between IDLE and BUSY.

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7	After Step 8
clk	0	0	1	0	1	0	1	0	1
reset	1	0	0	0	0	0	0	0	0
state	X	IDLE	IDLE	IDLE	BUSY	BUSY	IDLE	IDLE	IDLE
input_signal	0	0	1	1	0	0	0	0	0
next_state	X	IDLE	IDLE	BUSY	BUSY	IDLE	IDLE	IDLE	IDLE

Key Moments - 3 Insights

Why does the state update only on the rising edge of clk and not immediately when next_state changes?

Because the state register updates inside the clocked process only at rising_edge(clk), as shown in execution_table rows 2, 4, 6, and 8 where state changes after clk rises.

Why do we separate next_state logic from state update in two processes?

Separating next_state logic (combinational) from state update (sequential) avoids mixing timing and logic, making the design clearer and easier to debug, as seen in the two distinct processes in the code.

What happens if reset is '1' during a clock edge?

The state is immediately set to IDLE regardless of next_state, as shown in step 1 where reset=1 sets state to IDLE.

Visual Quiz - 3 Questions

Look at the execution_table at step 4. What is the state after the rising edge of clk?

A IDLE

B BUSY

C X (unknown)

D next_state

💡 Hint

Check the 'state (after)' column at step 4 in execution_table.

At which step does the reset signal cause the state to be set to IDLE?

A Step 3

B Step 2

C Step 1

D Step 5

💡 Hint

Look at the 'reset' and 'state (after)' columns in execution_table rows.

If input_signal is '1' at step 3, what is the next_state computed?

A BUSY

B IDLE or BUSY

C IDLE

D No change

💡 Hint

Refer to 'input_signal' and 'next_state (computed)' columns at step 3 in execution_table.

Concept Snapshot

Two-process FSM style in VHDL:
- Process 1: Sequential, updates state on rising clock edge and reset.
- Process 2: Combinational, computes next_state and outputs based on current state and inputs.
- Keeps state update and logic separate for clarity and synthesis.
- Reset asynchronously sets state.
- State changes only on clock edges.

Full Transcript

This visual execution shows a two-process FSM coding style in VHDL. The first process updates the state register on the rising edge of the clock or when reset is active. The second process computes the next state based on the current state and input signals. The execution table traces clock, reset, state before and after, input signals, and next state computation step-by-step. The variable tracker shows how each variable changes over time. Key moments clarify why state updates only on clock edges, why logic is separated, and the effect of reset. The quiz tests understanding of state changes, reset effect, and next state logic. The concept snapshot summarizes the two-process FSM style for quick reference.

Practice

1. In a two-process FSM coding style in VHDL, what is the main role of the first process?

easy

A. To update the current state on clock and reset signals

B. To decide the next state based on inputs

C. To generate output signals directly

D. To initialize variables outside the FSM

Solution

1. Step 1: Understand the two-process FSM structure

   The first process in a two-process FSM handles synchronous operations like updating the current state on clock edges and reset.

2. Step 2: Identify the role of the first process

   This process updates the current state register based on clock and reset signals, ensuring state changes happen synchronously.

3. Final Answer:

   To update the current state on clock and reset signals -> Option A

4. Quick Check:

   First process updates state [OK]

Hint: First process updates state on clock/reset [OK]

Common Mistakes:

• Confusing output logic with state update
• Thinking next state logic is in first process
• Assuming initialization happens in first process

2. Which of the following is the correct sensitivity list for the second process in a two-process FSM that decides next state and outputs?

easy

A. clk, reset

B. clk only

C. reset only

D. current_state, inputs

Solution

1. Step 1: Identify what triggers next state and output logic

   The second process is combinational and depends on current state and inputs to decide next state and outputs.

2. Step 2: Determine the sensitivity list

   It must include all signals that affect next state and outputs, which are current_state and inputs, not clock or reset.

3. Final Answer:

   current_state, inputs -> Option D

4. Quick Check:

   Second process sensitivity = current_state, inputs [OK]

Hint: Second process sensitive to state and inputs only [OK]

Common Mistakes:

• Including clock in second process sensitivity
• Using reset in sensitivity list incorrectly
• Leaving sensitivity list empty

3. Given the following VHDL code snippet for a two-process FSM, what will be the value of current_state after the rising edge of clk if reset is '0' and next_state is S1?

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

medium

A. S0

B. S1

C. Undefined

D. Remains previous state

Solution

1. Step 1: Analyze reset condition

   Reset is '0', so the reset block is skipped; no forced reset to S0.

2. Step 2: Analyze clock rising edge behavior

   On rising edge of clk, current_state is assigned next_state, which is S1.

3. Final Answer:

   S1 -> Option B

4. Quick Check:

   Reset '0' + rising edge = current_state = next_state [OK]

Hint: Reset '0' means state updates to next_state on clock [OK]

Common Mistakes:

• Assuming reset '0' resets state to S0
• Confusing next_state with current_state immediately
• Ignoring rising_edge condition

4. Identify the error in this two-process FSM snippet where the next state logic is incorrect:

process(current_state, input_signal)
begin
  case current_state is
    when S0 =>
      if input_signal = '1' then
        next_state <= S1;
      else
        next_state <= S0;
      end if;
    when S1 =>
      next_state <= S0;
  end case;
end process;

process(clk, reset)
begin
  if reset = '1' then
    current_state <= S0;
  elsif rising_edge(clk) then
    current_state <= next_state;
  end if;
end process;

medium

A. Sensitivity list missing clk and reset

B. Next state logic should be in clocked process

C. Missing default case in case statement

D. Using '<=' in combinational process instead of ':='

Solution

1. Step 1: Check the case statement coverage

   The case(current_state is) only specifies when S0 and when S1, but omits a catch-all 'when others' clause.

2. Step 2: Understand the consequence

   In a combinational process, incomplete case coverage infers latches on next_state, which is undesirable; it should be fully combinational logic. A default like 'when others => next_state <= current_state;' is needed.

3. Final Answer:

   Missing default case in case statement -> Option C

4. Quick Check:

   Missing when others => latch inferred [OK]

Hint: Case statements in combo processes need 'when others' [OK]

Common Mistakes:

• Omitting 'when others' in case statement
• Ignoring sensitivity list completeness
• Placing next state logic in clocked process

5. You want to design a two-process FSM in VHDL that has three states (IDLE, BUSY, DONE). The FSM should reset to IDLE, move to BUSY when start='1', and then to DONE after one clock cycle. Which of the following next state process code snippets correctly implements this behavior?

hard

A. process(current_state, start)
begin
case current_state is
when IDLE =>
if start = '1' then
next_state <= BUSY;
else
next_state <= IDLE;
end if;
when BUSY =>
next_state <= DONE;
when DONE =>
next_state <= IDLE;
end case;
end process;

B. process(clk, reset)
begin
if reset = '1' then
next_state <= IDLE;
elsif rising_edge(clk) then
if start = '1' then
next_state <= BUSY;
else
next_state <= DONE;
end if;
end if;
end process;

C. process(current_state)
begin
if start = '1' then
next_state <= BUSY;
else
next_state <= IDLE;
end if;
end process;

D. process(current_state, start)
begin
if current_state = IDLE and start = '1' then
next_state <= BUSY;
elsif current_state = BUSY then
next_state <= DONE;
end if;
end process;

Solution

1. Step 1: Check reset and state transitions

   The FSM resets to IDLE (handled in clocked process), so next_state logic must handle transitions from IDLE to BUSY on start='1', BUSY to DONE, and DONE to IDLE.

2. Step 2: Analyze next state logic options

   The correct code uses a combinational process with sensitivity to current_state and start, employing a case statement that fully covers all states with proper transitions: IDLE stays or goes to BUSY based on start, BUSY to DONE, DONE to IDLE. Other codes fail by using clocked process for next_state, missing inputs in sensitivity, incomplete state handling, or unassigned paths in conditional logic leading to latches.

3. Final Answer:

   The case statement with IDLE, BUSY, DONE transitions -> Option A

4. Quick Check:

   Case statement with all states and transitions [OK]

Hint: Use case statement covering all states for next state logic [OK]

Common Mistakes:

• Placing next state logic in clocked process
• Missing transitions for all states
• Ignoring start signal conditions