Sequence detector FSM in VHDL - Time & Space Complexity

Time Complexity: Sequence detector FSM in VHDL

O(n)

Understanding Time Complexity

We want to understand how the time needed to detect a sequence changes as the input grows.

How does the sequence detector's work scale with longer input streams?

Scenario Under Consideration

Analyze the time complexity of the following VHDL sequence detector code.

library ieee;
use ieee.std_logic_1164.all;

entity seq_detector is
  port(clk: in std_logic; reset: in std_logic; data_in: in std_logic; detected: out std_logic);
end seq_detector;

architecture behavior of seq_detector is
  type state_type is (S0, S1, S2, S3);
  signal state: state_type := S0;
begin
  process(clk, reset)
  begin
    if reset = '1' then
      state <= S0;
      detected <= '0';
    elsif rising_edge(clk) then
      case state is
        when S0 =>
          if data_in = '1' then
            state <= S1;
          else
            state <= S0;
          end if;
          detected <= '0';
        when S1 =>
          if data_in = '0' then
            state <= S2;
          else
            state <= S1;
          end if;
          detected <= '0';
        when S2 =>
          if data_in = '1' then
            state <= S3;
          else
            state <= S0;
          end if;
          detected <= '0';
        when S3 =>
          detected <= '1';
          if data_in = '1' then
            state <= S1;
          else
            state <= S0;
          end if;
      end case;
    end if;
  end process;
end behavior;

This code detects a specific bit pattern in a stream using a finite state machine.

Identify Repeating Operations

Look for repeated actions in the code.

• Primary operation: The process runs every clock cycle, checking the input bit and updating the state.
• How many times: Once per clock cycle, for each input bit in the stream.

How Execution Grows With Input

Each input bit causes one state update step.

Input Size (n)	Approx. Operations
10	10 state checks and updates
100	100 state checks and updates
1000	1000 state checks and updates

Pattern observation: The number of operations grows directly with the number of input bits.

Final Time Complexity

Time Complexity: O(n)

This means the time to detect sequences grows linearly with the input length.

Common Mistake

[X] Wrong: "The FSM checks multiple bits at once, so time grows slower than input size."

[OK] Correct: The FSM processes one bit per clock cycle, so time grows directly with input length.

Interview Connect

Understanding how FSMs scale helps you design efficient hardware and software that process streams smoothly.

Self-Check

"What if the FSM checked two bits per clock cycle? How would the time complexity change?"

Practice

1. What is the main purpose of a sequence detector FSM in VHDL?

easy

A. To perform arithmetic operations

B. To generate random numbers

C. To detect a specific pattern of bits in a serial input stream

D. To store large amounts of data

Solution

1. Step 1: Understand FSM role

   A sequence detector FSM is designed to watch input bits and identify a particular pattern.

2. Step 2: Match purpose with options

   Only To detect a specific pattern of bits in a serial input stream describes detecting a pattern in a bit stream, which matches the FSM's purpose.

3. Final Answer:

   To detect a specific pattern of bits in a serial input stream -> Option C

4. Quick Check:

   Sequence detector FSM = Pattern detection [OK]

Hint: FSMs track input patterns step-by-step [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM generates data
• Assuming FSM does math operations

2. Which VHDL construct is typically used to represent the states in a sequence detector FSM?

easy

A. signal

B. type (enumeration)

C. process

D. variable

Solution

1. Step 1: Identify how states are defined

   States in FSMs are usually defined as an enumerated type listing all possible states.

2. Step 2: Match with VHDL constructs

   Only 'type (enumeration)' fits this use, as it defines named states clearly.

3. Final Answer:

   type (enumeration) -> Option B

4. Quick Check:

   States = enumerated type [OK]

Hint: Use enumerated types to name FSM states clearly [OK]

Common Mistakes:

• Using signal or variable to define states directly
• Confusing process with state definition
• Not using enumeration for states

3. Given this VHDL snippet for a sequence detector FSM, what is the output when input sequence is 1,0,1,1?

type state_type is (S0, S1, S2, S3);
signal state: state_type := S0;
signal detected: std_logic := '0';

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when S0 =>
        if input_bit = '1' then
          state <= S1;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S1 =>
        if input_bit = '0' then
          state <= S2;
        else
          state <= S1;
        end if;
        detected <= '0';
      when S2 =>
        if input_bit = '1' then
          state <= S3;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S3 =>
        detected <= '1';
        state <= S0;
    end case;
  end if;
end process;

medium

A. detected = '1' after the second input

B. detected = '1' after the third input

C. detected = '0' for all inputs

D. detected = '1' after the fourth input

Solution

1. Step 1: Trace FSM states with inputs

   Input sequence: 1 -> S0 to S1, detected=0; 0 -> S1 to S2, detected=0; 1 -> S2 to S3, detected=0; 1 -> S3 outputs detected=1 and resets to S0.

2. Step 2: Identify when detection occurs

   Detection signal '1' is set only in state S3, which happens after the fourth input.

3. Final Answer:

   detected = '1' after the fourth input -> Option D

4. Quick Check:

   Detection on full pattern completion = after 4th input [OK]

Hint: Trace states stepwise with inputs to find detection timing [OK]

Common Mistakes:

• Assuming detection happens too early
• Ignoring state reset after detection
• Confusing input bits with states

4. Identify the error in this VHDL FSM snippet for a sequence detector:

process(clk)
begin
  if rising_edge(clk) then
    case state is
      when S0 =>
        if input_bit = '1' then
          state <= S1;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S1 =>
        if input_bit = '0' then
          state <= S2;
        else
          state <= S0; -- Error here
        end if;
        detected <= '0';
      when S2 =>
        if input_bit = '1' then
          state <= S3;
        else
          state <= S0;
        end if;
        detected <= '0';
      when S3 =>
        detected <= '1';
        state <= S0;
    end case;
  end if;
end process;

medium

A. Resetting to S0 on wrong input in S1 breaks overlapping detection

B. Missing clock sensitivity list

C. Detected signal should be '1' in all states

D. State S3 is not defined

Solution

1. Step 1: Analyze state transitions in S1

   Resetting to S0 on wrong input in S1 prevents the FSM from detecting overlapping sequences.

2. Step 2: Understand impact on sequence detection

   Proper overlapping detection requires transitioning to S1 or another state, not always S0, to catch patterns starting inside previous ones.

3. Final Answer:

   Resetting to S0 on wrong input in S1 breaks overlapping detection -> Option A

4. Quick Check:

   Overlapping detection needs careful state transitions [OK]

Hint: Check if FSM allows overlapping pattern detection [OK]

Common Mistakes:

• Ignoring overlapping sequences
• Assuming detected signal always '1'
• Forgetting clock edge sensitivity

5. You want to design a sequence detector FSM in VHDL that detects overlapping occurrences of the pattern "1011". Which approach correctly handles overlapping detection?

hard

A. After detecting full pattern, transition to the state representing the last '1' to allow overlap

B. Reset to initial state after detection to start fresh

C. Use a counter instead of states to track bits

D. Ignore overlapping sequences to simplify design

Solution

1. Step 1: Understand overlapping detection

   To detect overlapping patterns, FSM must not reset fully but keep track of partial matches.

2. Step 2: Choose correct state transition

   Transitioning to the state representing the last matched bit (here, last '1') allows the FSM to continue detecting overlapping sequences.

3. Final Answer:

   After detecting full pattern, transition to the state representing the last '1' to allow overlap -> Option A

4. Quick Check:

   Overlap detection = partial state retention [OK]

Hint: Keep FSM in partial match state after detection for overlaps [OK]

Common Mistakes:

• Resetting FSM fully after detection
• Using counters instead of states
• Ignoring overlapping patterns