Prescaler for clock division in VHDL - Mini Project: Build & Apply

Prescaler for Clock Division

📖 Scenario: You are designing a digital circuit that needs a slower clock signal derived from a faster input clock. This is common in electronics when you want to control timing for other parts of your system.

🎯 Goal: Build a simple VHDL prescaler that divides the input clock frequency by a fixed number using a counter.

📋 What You'll Learn

Create a signal to count clock pulses

Set a division factor as a constant

Implement a process that increments the counter on each clock rising edge

Toggle the output clock when the counter reaches the division factor

Reset the counter and output clock properly

💡 Why This Matters

🌍 Real World

Prescalers are used in digital circuits to slow down fast clock signals for timing control in microcontrollers, communication devices, and FPGA designs.

💼 Career

Understanding clock division and prescalers is essential for hardware engineers and FPGA developers working on timing-sensitive digital systems.

1

Create the clock counter signal

Declare a signal called counter of type integer range 0 to 9 inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prescaler is
    Port ( clk_in : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end prescaler;

architecture Behavioral of prescaler is
    -- Declare the counter signal here
    -- Your code here
begin

end Behavioral;

Hint

Signals are declared inside the architecture but before the begin keyword.

2

Set the division factor and output register

Declare a constant called DIV_FACTOR of type integer set to 10, and a signal called clk_out_reg of type STD_LOGIC initialized to '0' inside the architecture.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prescaler is
    Port ( clk_in : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end prescaler;

architecture Behavioral of prescaler is
    signal counter : integer range 0 to 9 := 0;
    -- Declare the DIV_FACTOR constant and clk_out_reg signal here
    -- Your code here
begin

end Behavioral;

Hint

Constants use the keyword constant. Signals use the keyword signal. Both go before begin.

3

Implement the prescaler process

Write a process sensitive to clk_in and reset. If reset is '1', set counter to 0 and clk_out_reg to '0'. On the rising edge of clk_in, increment counter. When counter reaches DIV_FACTOR - 1, reset counter to 0 and toggle clk_out_reg.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prescaler is
    Port ( clk_in : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end prescaler;

architecture Behavioral of prescaler is
    signal counter : integer range 0 to 9 := 0;
    constant DIV_FACTOR : integer := 10;
    signal clk_out_reg : STD_LOGIC := '0';
begin

    -- Write the prescaler process here
    -- Your code here

end Behavioral;

Hint

Use a process with sensitivity list (clk_in, reset). Use rising_edge(clk_in) to detect clock edges.

4

Output the divided clock signal

Assign the internal signal clk_out_reg to the output port clk_out using a concurrent signal assignment.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prescaler is
    Port ( clk_in : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk_out : out STD_LOGIC);
end prescaler;

architecture Behavioral of prescaler is
    signal counter : integer range 0 to 9 := 0;
    constant DIV_FACTOR : integer := 10;
    signal clk_out_reg : STD_LOGIC := '0';
begin

    process(clk_in, reset)
    begin
        if reset = '1' then
            counter <= 0;
            clk_out_reg <= '0';
        elsif rising_edge(clk_in) then
            if counter = DIV_FACTOR - 1 then
                counter <= 0;
                clk_out_reg <= not clk_out_reg;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    -- Assign clk_out_reg to clk_out here
    -- Your code here

end Behavioral;

Hint

Use a simple concurrent assignment to connect the internal signal to the output port.

Practice

1. What is the main purpose of a prescaler in VHDL clock division?

easy

A. To generate random clock pulses

B. To multiply the input clock frequency

C. To reset the clock signal

D. To divide a fast input clock into a slower output clock

Solution

1. Step 1: Understand the function of a prescaler

   A prescaler reduces the frequency of a fast clock by dividing it to create a slower clock signal.

2. Step 2: Compare options with the prescaler function

   Only To divide a fast input clock into a slower output clock correctly describes this division function; others describe unrelated actions.

3. Final Answer:

   To divide a fast input clock into a slower output clock -> Option D

4. Quick Check:

   Prescaler divides clock = To divide clock [OK]

Hint: Prescaler always divides clock frequency, never multiplies [OK]

Common Mistakes:

• Thinking prescaler multiplies clock frequency
• Confusing prescaler with reset function
• Assuming prescaler generates random pulses

2. Which VHDL code snippet correctly declares a counter signal for a prescaler?

easy

A. signal counter : integer range 0 to 99 := 0;

B. signal counter : std_logic_vector(7 downto 0) := '0';

C. signal counter : boolean := false;

D. signal counter : integer := '0';

Solution

1. Step 1: Identify proper signal type for counting

   Counting requires an integer with a defined range and initial value, as in signal counter : integer range 0 to 99 := 0;.

2. Step 2: Check other options for correctness

   signal counter : std_logic_vector(7 downto 0) := '0'; uses std_logic_vector but initializes incorrectly with a single quote; signal counter : boolean := false; uses boolean which can't count; signal counter : integer := '0'; assigns a character to integer, which is invalid.

3. Final Answer:

   signal counter : integer range 0 to 99 := 0; -> Option A

4. Quick Check:

   Integer counter with range and init = Correct declaration [OK]

Hint: Use integer with range and initial value for counters [OK]

Common Mistakes:

• Using std_logic_vector without proper initialization
• Using boolean type for counting
• Assigning character literals to integer signals

3. Given this VHDL process for a prescaler with a max count of 3:

process(clk, reset)
begin
  if reset = '1' then
    counter <= 0;
    clk_out <= '0';
  elsif rising_edge(clk) then
    if counter = 3 then
      counter <= 0;
      clk_out <= not clk_out;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

What is the frequency division factor of clk_out relative to clk?

medium

A. 4

B. 8

C. 6

D. 3

Solution

1. Step 1: Understand counter behavior

   The counter counts from 0 to 3, so it counts 4 clock cycles before toggling clk_out.

2. Step 2: Calculate total division factor

   Since clk_out toggles every 4 input clocks, one full cycle of clk_out is 8 input clocks (4 up, 4 down).

3. Final Answer:

   8 -> Option B

4. Quick Check:

   Toggle every 4 clocks means full period 8 clocks [OK]

Hint: Multiply count by 2 for full output clock period [OK]

Common Mistakes:

• Using counter max value as division factor directly
• Forgetting clk_out toggles, doubling period
• Counting only half the clock cycles

4. Identify the error in this prescaler process code:

process(clk, reset)
begin
  if reset = '1' then
    counter <= 0;
    clk_out <= '0';
  elsif rising_edge(clk) then
    if counter = 4 then
      counter <= 0;
      clk_out <= not clk_out;
    else
      counter <= counter + 1;
    end if;
  end if;
end process;

Assuming counter is declared as integer range 0 to 3, what will happen?

medium

A. Counter never reaches 4, so clk_out never toggles

B. Counter resets correctly at 4

C. Runtime error due to counter overflow

D. clk_out toggles every clock cycle

Solution

1. Step 1: Check counter range and comparison

   The counter is declared with range 0 to 3, but the code checks if counter = 4, which is outside the range.

2. Step 2: Understand effect of out-of-range value

   Since counter can only count up to 3, it will never equal 4, so the condition is never true and clk_out never toggles.

3. Final Answer:

   Counter never reaches 4, so clk_out never toggles -> Option A

4. Quick Check:

   Counter max 3 but checks 4 = Condition never met [OK]

Hint: Check counter max matches comparison value [OK]

Common Mistakes:

• Ignoring counter range limits
• Assuming counter can reach out-of-range values
• Thinking clk_out toggles without counter reset

5. You want to design a prescaler in VHDL that divides a 50 MHz clock down to 1 kHz. Which counter range is closest to the correct choice?
Use the formula: division factor = 50,000,000 / 1,000 = 50,000.
Remember the output clock toggles every time the counter reaches max and resets.

hard

A. signal counter : integer range 0 to 99999 := 0;

B. signal counter : integer range 0 to 49999 := 0;

C. signal counter : integer range 0 to 24999 := 0;

D. signal counter : integer range 0 to 12499 := 0;

Solution

1. Step 1: Calculate division factor for toggling

   The full division factor is 50,000, but clk_out toggles every time counter reaches max, so counter max = 50,000 / 2 = 25,000.

2. Step 2: Choose closest counter range

   Since counting starts at 0, range should be 0 to 24,999 to count 25,000 cycles.

3. Final Answer:

   signal counter : integer range 0 to 24999 := 0; -> Option C

4. Quick Check:

   Divide by 2 for toggle count = 24999 max [OK]

Hint: Divide total count by 2 for toggle max count [OK]

Common Mistakes:

• Using full division factor as counter max
• Not dividing by 2 for toggle behavior
• Choosing incorrect range limits