Challenge - 5 Problems
VHDL Package Mastery
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❓ Predict Output
intermediateOutput of a function call from a package
What is the output of the following VHDL code snippet when the function
add_one is called with input 5?VHDL
package math_pkg is function add_one(x : integer) return integer; end package; package body math_pkg is function add_one(x : integer) return integer is begin return x + 1; end function; end package body; architecture behavior of test is signal result : integer; begin process begin result <= math_pkg.add_one(5); wait; end process; end behavior;
Attempts:
2 left
💡 Hint
Remember that the function adds 1 to the input value.
✗ Incorrect
The function
add_one defined in the package adds 1 to the input integer. Calling it with 5 returns 6, which is assigned to result.❓ Predict Output
intermediateProcedure call effect on signal in package
Given the following VHDL code, what is the value of signal
out_val after the procedure set_value is called with input 10?VHDL
package util_pkg is procedure set_value(signal s : out integer; val : integer); end package; package body util_pkg is procedure set_value(signal s : out integer; val : integer) is begin s <= val; end procedure; end package body; architecture behavior of test is signal out_val : integer := 0; begin process begin util_pkg.set_value(out_val, 10); wait; end process; end behavior;
Attempts:
2 left
💡 Hint
Procedures can assign values to signals passed as out parameters.
✗ Incorrect
The procedure
set_value assigns the input value to the signal passed as an out parameter. Calling it with 10 sets out_val to 10.🧠 Conceptual
advancedError caused by missing package body for function
What error will occur if a function declared in a VHDL package is used in design but its body is missing in the package body?
Attempts:
2 left
💡 Hint
Think about what happens when the function implementation is missing.
✗ Incorrect
If the function is declared but not defined in the package body, the compiler accepts the declaration but the linker cannot find the function implementation, causing a linker error.
❓ Predict Output
advancedOutput of recursive function in package
What is the output of the following recursive function
factorial defined in a package when called with input 4?VHDL
package math_pkg is function factorial(n : integer) return integer; end package; package body math_pkg is function factorial(n : integer) return integer is begin if n = 0 then return 1; else return n * factorial(n - 1); end if; end function; end package body; architecture behavior of test is signal result : integer; begin process begin result <= math_pkg.factorial(4); wait; end process; end behavior;
Attempts:
2 left
💡 Hint
Factorial of 4 is 4*3*2*1.
✗ Incorrect
The recursive function calculates factorial correctly. factorial(4) = 4*3*2*1 = 24.
🔧 Debug
expertIdentify the error in procedure parameter passing
What error will the following VHDL code produce when compiling, considering the procedure parameter mode?
VHDL
package util_pkg is procedure update_val(signal s : in integer; val : integer); end package; package body util_pkg is procedure update_val(signal s : in integer; val : integer) is begin s <= val; end procedure; end package body; architecture behavior of test is signal data : integer := 0; begin process begin util_pkg.update_val(data, 5); wait; end process; end behavior;
Attempts:
2 left
💡 Hint
Signals declared as 'in' mode cannot be assigned inside procedures.
✗ Incorrect
The procedure parameter
s is declared as in mode, which means it is read-only. Assigning to it causes a compilation error.