D flip-flop with synchronous reset in VHDL - Step-by-Step Execution

Concept Flow - D flip-flop with synchronous reset

Clock Rising Edge

↓

Check Reset Signal

↓

Set Q=0

↓

Hold Q Until Next Clock

On each rising clock edge, the flip-flop checks the reset signal. If reset is active, output Q is set to 0; otherwise, Q takes the value of input D.

Execution Sample

VHDL

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      Q <= '0';
    else
      Q <= D;
    end if;
  end if;
end process;

This VHDL process updates output Q on the rising edge of clk, resetting Q to 0 if reset is high, else copying input D.

Execution Table

Step	clk	reset	D	Condition	Q (before)	Q (after)	Action
1	0	0	0	No rising edge	X	X	No change
2	rising edge	0	1	reset='0' -> Q=D	X	1	Q set to D=1
3	1	0	1	No rising edge	1	1	No change
4	falling edge	1	0	No rising edge	1	1	No change
5	rising edge	1	0	reset='1' -> Q=0	1	0	Q reset to 0
6	1	0	1	No rising edge	0	0	No change
7	rising edge	0	0	reset='0' -> Q=D	0	0	Q set to D=0
8	rising edge	0	1	reset='0' -> Q=D	0	1	Q set to D=1

💡 Simulation ends after step 8; process reacts only on rising clock edges.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8
clk	0	rising edge	1	falling edge	rising edge	1	rising edge	rising edge	rising edge
reset	0	0	0	1	1	0	0	0	0
D	0	1	1	0	0	1	0	1	1
Q	X	X	1	1	1	0	0	0	1

Key Moments - 3 Insights

Why does Q only change on the rising edge of clk and not on falling edge or when clk is stable?

Because the process uses 'if rising_edge(clk)' condition (see execution_table rows 1, 3, 4), Q updates only at rising edges, ignoring other clk changes.

What happens to Q when reset is '1' during a rising clock edge?

Q is synchronously reset to '0' on that rising edge (see execution_table row 5), overriding the D input.

Why does Q hold its value when reset is '0' but clk is not rising?

Because the process only updates Q on rising edges; without a rising edge, Q remains unchanged (see rows 1, 3, 4, 6).

Visual Quiz - 3 Questions

Look at the execution table, what is the value of Q after step 2?

A 'X'

B '0'

C '1'

D No change

💡 Hint

Check Q (after) column in row 2 where reset='0' and D='1'.

At which step does the reset signal cause Q to be set to '0'?

A Step 5

B Step 3

C Step 4

D Step 7

💡 Hint

Look for reset='1' and Q changing to '0' in the execution_table.

If reset was '1' at step 8, what would Q be after that step?

A '1'

B '0'

C No change

D 'X'

💡 Hint

Recall that reset='1' forces Q to '0' on rising edge (see step 5).

Concept Snapshot

D flip-flop with synchronous reset in VHDL:
- On rising clock edge, check reset.
- If reset='1', set Q to '0'.
- Else, set Q to D input.
- Q holds value between clock edges.
- Synchronous reset means reset acts only on clock edge.

Full Transcript

This visual execution shows a D flip-flop with synchronous reset in VHDL. The flip-flop updates output Q only on the rising edge of the clock signal. When the reset signal is high ('1') during a rising clock edge, Q is set to '0'. Otherwise, Q takes the value of input D. Between clock edges, Q holds its previous value. The execution table traces each step with clock, reset, D, and Q values, showing when Q changes or holds. Key moments clarify why Q changes only on rising edges and how reset affects Q synchronously. The quiz tests understanding of Q's value changes and reset behavior. This helps beginners see how synchronous reset works in a D flip-flop.

Practice

1.

What does a synchronous reset do in a D flip-flop?

easy

A. It disables the clock signal.

B. It clears the stored data immediately when reset is active.

C. It stores data continuously without any reset.

D. It clears the stored data only at the clock's rising edge.

Solution

1. Step 1: Understand synchronous reset behavior

   A synchronous reset affects the flip-flop only during the clock's active edge, not immediately.

2. Step 2: Compare with asynchronous reset

   Asynchronous reset clears data immediately, but synchronous reset waits for the clock edge.

3. Final Answer:

   It clears the stored data only at the clock's rising edge. -> Option D

4. Quick Check:

   Synchronous reset = clears data on clock edge [OK]

Hint: Synchronous reset acts only on clock edge, not instantly. [OK]

Common Mistakes:

• Confusing synchronous with asynchronous reset
• Thinking reset works immediately without clock
• Assuming reset disables clock

2.

Which of the following is the correct VHDL sensitivity list for a D flip-flop with synchronous reset?

process(???)

easy

A. clk, reset

B. clk

C. reset

D. clk, reset, d

Solution

1. Step 1: Identify signals triggering the process

   For synchronous reset, only the clock edge triggers the process, so only 'clk' is in the sensitivity list.

2. Step 2: Understand synchronous reset inside process

   The reset is checked inside the clock edge condition, so it does not go in sensitivity list.

3. Final Answer:

   clk -> Option B

4. Quick Check:

   Synchronous reset uses only clock in sensitivity list [OK]

Hint: Only clock in sensitivity list for synchronous reset. [OK]

Common Mistakes:

• Including reset in sensitivity list for synchronous reset
• Adding data input 'd' to sensitivity list
• Confusing asynchronous reset sensitivity

3.

Given this VHDL code snippet for a D flip-flop with synchronous reset, what is the output q after the rising edge of clk if reset = '1' and d = '0'?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. '0'

B. '1'

C. No change

D. Undefined

Solution

1. Step 1: Check reset condition at clock edge

   At rising edge, reset is '1', so q is set to '0'.

2. Step 2: Ignore data input since reset is active

   Because reset is active, q does not take value from d.

3. Final Answer:

   '0' -> Option A

4. Quick Check:

   Reset '1' sets q to '0' on clock edge [OK]

Hint: Reset '1' overrides data input at clock edge. [OK]

Common Mistakes:

• Ignoring reset and taking d value
• Thinking output changes immediately without clock
• Confusing synchronous with asynchronous reset

4.

Identify the error in this VHDL code for a D flip-flop with synchronous reset:

process(clk, reset)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';
    else
      q <= d;
    end if;
  end if;
end process;

medium

A. Reset should not be in the sensitivity list for synchronous reset.

B. Missing else statement for reset condition.

C. rising_edge(clk) should be replaced with falling_edge(clk).

D. Data input 'd' should be in sensitivity list.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset requires only clock in sensitivity list, not reset.

2. Step 2: Understand why reset is excluded

   Reset is checked inside clock edge condition, so including it causes unnecessary triggers.

3. Final Answer:

   Reset should not be in the sensitivity list for synchronous reset. -> Option A

4. Quick Check:

   Synchronous reset sensitivity list = clock only [OK]

Hint: Exclude reset from sensitivity list for synchronous reset. [OK]

Common Mistakes:

• Including reset in sensitivity list
• Changing clock edge without reason
• Adding data input to sensitivity list

5.

You want to design a D flip-flop with synchronous reset that sets output q to '1' when reset is active instead of '0'. Which code modification achieves this?

process(clk)
begin
  if rising_edge(clk) then
    if reset = '1' then
      q <= '0';  -- change this line
    else
      q <= d;
    end if;
  end if;
end process;

hard

A. Replace if reset = '1' with if reset = '0'

B. Add q <= '1'; before the if statement

C. Change q <= '0'; to q <= '1';

D. Move reset check outside the clock edge condition

Solution

1. Step 1: Identify reset output assignment

   The line q <= '0'; sets q to zero on reset.

2. Step 2: Modify reset output to '1'

   Changing this line to q <= '1'; sets q to one when reset is active.

3. Final Answer:

   Change q <= '0'; to q <= '1'; -> Option C

4. Quick Check:

   Reset output changed by modifying assignment line [OK]

Hint: Change reset assignment line to desired output value. [OK]

Common Mistakes:

• Adding assignment outside clock edge
• Reversing reset condition incorrectly
• Adding redundant assignments