D flip-flop with asynchronous reset in VHDL - Mini Project: Build & Apply

D flip-flop with asynchronous reset

📖 Scenario: You are designing a simple digital circuit component called a D flip-flop. This flip-flop stores a single bit of data and can be reset asynchronously, meaning it can be cleared immediately when a reset signal is active, regardless of the clock.

🎯 Goal: Build a VHDL code for a D flip-flop with an asynchronous reset input. The flip-flop should store the input data on the rising edge of the clock and reset the output to 0 immediately when the reset is active.

📋 What You'll Learn

Create a VHDL entity named DFlipFlop with inputs D, CLK, and RESET, and output Q.

Add a signal declaration for the output Q as a std_logic.

Write a process that triggers on the rising edge of CLK or when RESET is active.

Inside the process, asynchronously reset Q to '0' when RESET is '1', else on rising clock edge assign D to Q.

Print the final VHDL code.

💡 Why This Matters

🌍 Real World

D flip-flops are basic building blocks in digital electronics used for storing bits in registers, memory, and state machines.

💼 Career

Understanding how to write VHDL code for flip-flops is essential for FPGA and ASIC design engineers working on digital hardware.

1

Create the entity and architecture skeleton

Write the VHDL entity named DFlipFlop with inputs D, CLK, and RESET all of type std_logic, and output Q of type std_logic. Also start the architecture named Behavior.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Declare entity DFlipFlop with inputs D, CLK, RESET and output Q
entity DFlipFlop is
    Port (
        D : in std_logic;
        CLK : in std_logic;
        RESET : in std_logic;
        Q : out std_logic
    );
end DFlipFlop;

architecture Behavior of DFlipFlop is
begin
    -- Your code here
end Behavior;

Hint

Start by declaring the entity with the exact port names and types. Then open the architecture block.

2

Declare internal signal for output

Inside the architecture Behavior, declare a signal named Q_reg of type std_logic to hold the flip-flop state internally.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
    Port (
        D : in std_logic;
        CLK : in std_logic;
        RESET : in std_logic;
        Q : out std_logic
    );
end DFlipFlop;

architecture Behavior of DFlipFlop is
    signal Q_reg : std_logic;
    -- Your code here
begin

end Behavior;

Hint

Declare the signal inside the architecture but before the begin keyword.

3

Write the process for asynchronous reset and data capture

Write a process named flipflop_proc that triggers on the rising edge of CLK or when RESET changes. Inside, if RESET is '1', set Q_reg to '0'. Otherwise, on rising edge of CLK, assign D to Q_reg. Also assign Q_reg to output Q outside the process.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
    Port (
        D : in std_logic;
        CLK : in std_logic;
        RESET : in std_logic;
        Q : out std_logic
    );
end DFlipFlop;

architecture Behavior of DFlipFlop is
    signal Q_reg : std_logic;
begin
    process(CLK, RESET)
    begin
        -- Your code here
    end process;
    Q <= Q_reg;
end Behavior;

Hint

Use a process sensitive to CLK and RESET. Check RESET first for asynchronous reset, then use rising_edge(CLK) to capture D.

4

Print the complete VHDL code

Print the entire VHDL code for the D flip-flop with asynchronous reset exactly as written in the architecture Behavior.

VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DFlipFlop is
    Port (
        D : in std_logic;
        CLK : in std_logic;
        RESET : in std_logic;
        Q : out std_logic
    );
end DFlipFlop;

architecture Behavior of DFlipFlop is
    signal Q_reg : std_logic;
begin
    process(CLK, RESET)
    begin
        if RESET = '1' then
            Q_reg <= '0';
        elsif rising_edge(CLK) then
            Q_reg <= D;
        end if;
    end process;
    Q <= Q_reg;
end Behavior;

-- Your code here to print the code

Hint

Use report statements to print each line of the VHDL code exactly as written.

Practice

1. What is the main function of the asynchronous reset in a D flip-flop?

easy

A. It stores data only on the rising edge of the clock.

B. It immediately clears the output regardless of the clock.

C. It delays the output change until the next clock edge.

D. It toggles the output on every clock cycle.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset clears the output immediately, without waiting for the clock.

2. Step 2: Compare with clocked behavior

   Unlike clocked data storage, asynchronous reset acts instantly when active.

3. Final Answer:

   It immediately clears the output regardless of the clock. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Asynchronous reset acts instantly, ignoring clock [OK]

Common Mistakes:

• Confusing asynchronous reset with clocked data storage
• Thinking reset waits for clock edge
• Assuming reset toggles output

2. Which of the following VHDL code snippets correctly declares a D flip-flop with asynchronous reset?

easy

A. process(clk) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

C. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

D. process(reset) begin if reset = '1' then q <= '0'; end if; end process;

Solution

1. Step 1: Check sensitivity list for asynchronous reset

   Asynchronous reset requires reset signal in sensitivity list along with clock.

2. Step 2: Verify reset condition before clock edge

   Reset condition must be checked first, then clock edge for data update.

3. Final Answer:

   process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; -> Option C

4. Quick Check:

   Reset in sensitivity list + reset checked first = correct async reset [OK]

Hint: Async reset needs reset in sensitivity list and checked first [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Checking reset inside clock edge condition
• Using only reset process without clock

3. Given this VHDL process for a D flip-flop with asynchronous reset:

process(clk, reset)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

If reset is '0', d is '1', and a rising edge on clk occurs, what will be the value of q?

medium

A. Undefined

B. '0'

C. No change

D. '1'

Solution

1. Step 1: Check reset signal

   Reset is '0', so asynchronous reset does not clear output.

2. Step 2: Check clock edge and data input

   Rising edge on clk triggers q to take value of d, which is '1'.

3. Final Answer:

   '1' -> Option D

4. Quick Check:

   Reset '0' + rising clk + d='1' means q='1' [OK]

Hint: Reset '0' means normal clocked data update [OK]

Common Mistakes:

• Assuming reset clears output when '0'
• Ignoring clock edge
• Thinking output stays unchanged

4. Identify the error in this VHDL code for a D flip-flop with asynchronous reset:

process(clk)
begin
  if reset = '1' then
    q <= '0';
  elsif rising_edge(clk) then
    q <= d;
  end if;
end process;

medium

A. Reset signal is not in the sensitivity list for asynchronous reset.

B. The reset condition should be checked after the clock edge.

C. The process should not use rising_edge(clk) for a flip-flop.

D. The output q should be assigned using <= only inside clock edge.

Solution

1. Step 1: Check sensitivity list for asynchronous reset

   Asynchronous reset requires reset signal in sensitivity list to respond immediately.

2. Step 2: Analyze reset checking position

   Reset is checked before clock edge, which is correct, but missing reset in sensitivity list causes error.

3. Final Answer:

   Reset signal is not in the sensitivity list for asynchronous reset. -> Option A

4. Quick Check:

   Async reset needs reset in sensitivity list [OK]

Hint: Async reset must be in sensitivity list [OK]

Common Mistakes:

• Omitting reset from sensitivity list
• Checking reset after clock edge
• Misusing rising_edge for flip-flop

5. You want to design a D flip-flop with asynchronous reset that sets output q to '0' immediately when reset is '1', and otherwise updates q with d on the rising edge of clk. Which VHDL process correctly implements this behavior and avoids unintended latches?

hard

A. process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process;

B. process(clk) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

C. process(reset) begin if reset = '1' then q <= '0'; else q <= d; end if; end process;

D. process(clk, reset) begin if rising_edge(clk) then if reset = '1' then q <= '0'; else q <= d; end if; end if; end process;

Solution

1. Step 1: Check sensitivity list for asynchronous reset

   Reset and clk must be in sensitivity list for asynchronous reset to work properly.

2. Step 2: Verify reset checked before clock edge

   Reset condition checked first ensures immediate clearing without waiting for clock.

3. Step 3: Confirm no latches created

   All outputs assigned in all branches, so no unintended latches occur.

4. Final Answer:

   process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then q <= d; end if; end process; -> Option A

5. Quick Check:

   Reset in sensitivity + reset first + all assignments = correct async reset flip-flop [OK]

Hint: Reset in sensitivity list and checked first avoids latches [OK]

Common Mistakes:

• Checking reset inside clock edge (not async)
• Missing reset in sensitivity list
• Creating latches by incomplete assignments