Avoiding unintended latch inference in VHDL - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare a process sensitive to clock and reset signals.

VHDL

process([1])
begin
  if reset = '1' then
    output <= '0';
  elsif rising_edge(clock) then
    output <= input_signal;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Ainput_signal

Bclock, reset

Creset

Dclock

Attempts:

3 left

💡 Hint

Common Mistakes

Leaving out reset from the sensitivity list causes the process not to respond to reset changes.

Including signals unrelated to the process sensitivity.

The process must be sensitive to both clock and reset signals to avoid unintended latches.

2fill in blank

medium

Complete the code to assign a default value to avoid latch inference.

VHDL

process(clock)
begin
  if rising_edge(clock) then
    output_signal <= [1];
  end if;
end process;

Drag options to blanks, or click blank then click option'

Ainput_signal

Boutput_signal

C'Z'

D'0'

Attempts:

3 left

💡 Hint

Common Mistakes

Not assigning a value within the rising_edge block causes latch inference.

Using high impedance 'Z' as default in synchronous logic.

Assigning a default value like '0' ensures the signal is always driven, preventing latch inference.

3fill in blank

hard

Fix the error in the process to avoid unintended latch inference by completing the missing assignment.

VHDL

process(clock)
begin
  if rising_edge(clock) then
    if enable = '1' then
      output_signal <= input_signal;
    else
      [1];
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aoutput_signal <= output_signal

Boutput_signal <= '0'

Coutput_signal <= input_signal

Dnull

Attempts:

3 left

💡 Hint

Common Mistakes

Leaving the else branch empty causes latch inference.

Assigning a constant value may not preserve the intended behavior.

Assigning output_signal to itself in the else branch prevents latch inference by ensuring it is always assigned.

4fill in blank

hard

Fill both blanks to complete the combinational process without causing latch inference.

VHDL

process(a, b)
begin
  if a = '1' then
    y <= [1];
  else
    y <= [2];
  end if;
end process;

Drag options to blanks, or click blank then click option'

A'1'

B'0'

C'Z'

Dy

Attempts:

3 left

💡 Hint

Common Mistakes

Leaving one branch without assignment causes latch inference.

Using 'Z' in combinational logic can cause unexpected behavior.

Assigning '1' and '0' in all branches ensures y is always assigned, avoiding latch inference.

5fill in blank

hard

Fill all three blanks to complete the process that avoids unintended latch inference by proper default assignment and sensitivity list.

VHDL

process([1])
begin
  if reset = '1' then
    output <= '0';
  elsif rising_edge([2]) then
    if enable = '1' then
      output <= input_signal;
    else
      output <= [3];
    end if;
  end if;
end process;

Drag options to blanks, or click blank then click option'

Aclock

C'0'

Dclock, reset

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting reset from sensitivity list.

Using wrong signal in rising_edge.

Not assigning output in else branch.

The sensitivity list must include reset; rising_edge uses clock; default assignment in else is '0' to avoid latches.

Practice

1. What causes unintended latch inference in a VHDL process?

easy

A. Not assigning a signal in all possible branches inside a process

B. Using only combinational logic without clocks

C. Assigning signals only in the clocked part of a process

D. Using variables instead of signals

Solution

1. Step 1: Understand latch inference

   In VHDL, if a signal is not assigned in every possible condition inside a process, the synthesizer infers a latch to hold the previous value.

2. Step 2: Identify cause of unintended latches

   Missing assignments in some branches cause the tool to create latches to remember old values, which is usually unintended.

3. Final Answer:

   Not assigning a signal in all possible branches inside a process -> Option A

4. Quick Check:

   Missing assignments = unintended latch [OK]

Hint: Always assign signals in every branch to avoid latches [OK]

Common Mistakes:

• Thinking latches come from clocked processes only
• Assuming variables cause latches
• Believing combinational logic never infers latches

2. Which VHDL code snippet correctly avoids unintended latch inference?

easy

A. process(a, b) begin if a = '1' then y <= '1'; else null; end if; end process;

B. process(a, b) begin if a = '1' then y <= '1'; end if; end process;

C. process(a, b) begin y <= '0'; if a = '1' then y <= '1'; end if; end process;

D. process(a, b) begin if a = '1' then y <= '1'; elsif b = '1' then y <= '0'; end if; end process;

Solution

1. Step 1: Check assignments in all branches

   process(a, b) begin y <= '0'; if a = '1' then y <= '1'; end if; end process; assigns y <= '0' before the if, so y is always assigned regardless of conditions.

2. Step 2: Compare other options

   process(a, b) begin if a = '1' then y <= '1'; end if; end process; misses assignment when a /= '1', causing latch. process(a, b) begin if a = '1' then y <= '1'; else null; end if; end process; uses null which does not assign y. process(a, b) begin if a = '1' then y <= '1'; elsif b = '1' then y <= '0'; end if; end process; misses assignment if neither condition is true.

3. Final Answer:

   process(a, b) begin y <= '0'; if a = '1' then y <= '1'; end if; end process; -> Option C

4. Quick Check:

   Default assignment before conditions = no latch [OK]

Hint: Use default assignments before conditions to prevent latches [OK]

Common Mistakes:

• Using null instead of assigning signals
• Not covering all conditions with assignments
• Assuming else branch is optional

3. What is the output of this VHDL process for input a = '0' and b = '1'?

process(a, b) begin if a = '1' then y <= '1'; elsif b = '1' then y <= '0'; end if; end process;

medium

A. y = '0'

B. y = '1'

C. y retains previous value (latch inferred)

D. y = 'Z' (high impedance)

Solution

1. Step 1: Analyze conditions for a='0', b='1'

   The first if (a='1') is false, so skip to elsif (b='1'), which is true, so y <= '0'.

2. Step 2: Note latch inference overall

   A latch is inferred because the case a='0', b='0' has no assignment. However, for the given inputs a='0', b='1', y is explicitly assigned '0'.

3. Final Answer:

   y = '0' -> Option A

4. Quick Check:

   Taken branch assigns despite inferred latch [OK]

Hint: Check if all input combos assign output to avoid latches [OK]

Common Mistakes:

• Assuming y always updates without default assignment
• Ignoring latch inference on missing else
• Confusing latch with high impedance

4. Identify the error causing unintended latch inference in this code:

process(clk, reset) begin if reset = '1' then q <= '0'; elsif rising_edge(clk) then if enable = '1' then q <= d; end if; end if; end process;

medium

A. Using rising_edge(clk) incorrectly

B. Missing assignment to q when enable /= '1'

C. Incorrect sensitivity list

D. Missing reset condition

Solution

1. Step 1: Check assignments inside clocked process

   When enable = '1', q <= d assigned. But when enable /= '1', q is not assigned any value.

2. Step 2: Understand latch inference in clocked process

   Not assigning q in all branches inside clocked process causes latch inference to hold previous q value.

3. Final Answer:

   Missing assignment to q when enable /= '1' -> Option B

4. Quick Check:

   All branches must assign signals to avoid latches [OK]

Hint: Assign signals in every if-else branch inside clocked processes [OK]

Common Mistakes:

• Assuming reset covers all cases
• Ignoring else branch after enable check
• Thinking sensitivity list causes latch

5. You want to design a combinational process that outputs z based on inputs a and b. Which code snippet best avoids unintended latch inference while implementing:
if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; else z <= 'X'; end if;

hard

A. process(a, b) begin if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; end if; end process;

B. process(a, b) begin if a = '1' then z <= '1'; if b = '1' then z <= '0'; else z <= 'X'; end if; end if; end process;

C. process(a, b) begin if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; else null; end if; end process;

D. process(a, b) begin z <= 'X'; if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; end if; end process;

Solution

1. Step 1: Check for default assignment

   process(a, b) begin z <= 'X'; if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; end if; end process; assigns z <= 'X' before conditions, ensuring z always has a value.

2. Step 2: Verify conditional assignments

   Then it overrides z if a='1' or b='1', covering all cases without missing assignments.

3. Step 3: Analyze other options

   process(a, b) begin if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; end if; end process; misses else assignment causing latch. process(a, b) begin if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; else null; end if; end process; uses null which does not assign z. process(a, b) begin if a = '1' then z <= '1'; if b = '1' then z <= '0'; else z <= 'X'; end if; end if; end process; has nested ifs causing logic errors and possible latch.

4. Final Answer:

   process(a, b) begin z <= 'X'; if a = '1' then z <= '1'; elsif b = '1' then z <= '0'; end if; end process; -> Option D

5. Quick Check:

   Default assignment before conditions prevents latches [OK]

Hint: Set default output before conditions to cover all cases [OK]

Common Mistakes:

• Omitting else branch or default assignment
• Using null instead of assigning signal
• Incorrect nested if causing missed assignments