UART transmitter module in Verilog - Step-by-Step Execution

Concept Flow - UART transmitter module

Idle State: TX line high

↓

Start Bit: TX line low

↓

Send Data Bits: LSB to MSB

↓

Send Stop Bit: TX line high

↓

Return to Idle

The UART transmitter waits idle with TX line high, sends a start bit low, then sends data bits one by one, followed by a stop bit high, then returns to idle.

Execution Sample

Verilog

module uart_tx(
  input clk, input rst, input tx_start,
  input [7:0] tx_data, output reg tx
);
// simplified UART transmitter logic
endmodule

This module sends 8-bit data serially over TX line with start and stop bits.

Execution Table

Step	State	Bit Index	TX Line	Action	Notes
1	Idle	-	1	Wait for tx_start	TX line idle high
2	Start Bit	-	0	Send start bit	Start bit is low
3	Data Bit 0	0	0	Send LSB of data	Sending bit 0 of tx_data
4	Data Bit 1	1	1	Send bit 1	Sending bit 1 of tx_data
5	Data Bit 2	2	0	Send bit 2	Sending bit 2 of tx_data
6	Data Bit 3	3	1	Send bit 3	Sending bit 3 of tx_data
7	Data Bit 4	4	0	Send bit 4	Sending bit 4 of tx_data
8	Data Bit 5	5	0	Send bit 5	Sending bit 5 of tx_data
9	Data Bit 6	6	1	Send bit 6	Sending bit 6 of tx_data
10	Data Bit 7	7	1	Send MSB	Sending bit 7 of tx_data
11	Stop Bit	-	1	Send stop bit	Stop bit is high
12	Idle	-	1	Return to idle	Ready for next tx_start

💡 All bits sent, stop bit transmitted, return to idle state

Variable Tracker

Variable	Start	After Step 2	After Step 3	After Step 4	After Step 5	After Step 6	After Step 7	After Step 8	After Step 9	After Step 10	After Step 11	Final
state	Idle	Start Bit	Data Bit 0	Data Bit 1	Data Bit 2	Data Bit 3	Data Bit 4	Data Bit 5	Data Bit 6	Data Bit 7	Stop Bit	Idle
bit_index	-	0	1	2	3	4	5	6	7	8	-	-
tx	1	0	0	1	0	1	0	0	1	1	1	1

Key Moments - 3 Insights

Why is the TX line low during the start bit?

The start bit signals the beginning of data transmission by pulling the TX line low, as shown in execution_table step 2.

How does the transmitter know which data bit to send next?

The bit_index variable increments each step during data bits (steps 3 to 10), selecting the correct bit from tx_data.

Why is the stop bit high after sending all data bits?

The stop bit returns the TX line to high to mark the end of transmission, as seen in step 11, preparing for the next byte.

Visual Quiz - 3 Questions

Look at the execution table, what is the TX line value during the start bit?

A 1

B 0

C -

D Depends on data

💡 Hint

Check execution_table row with State 'Start Bit' and column 'TX Line'

At which step does the transmitter send the most significant bit (bit 7)?

A Step 8

B Step 11

C Step 10

D Step 7

💡 Hint

Look at execution_table rows with 'Data Bit' states and bit_index values

If tx_start is never asserted, what happens to the TX line?

A It stays high

B It toggles randomly

C It stays low

D It sends stop bits repeatedly

💡 Hint

Refer to variable_tracker 'tx' value at 'Start' and 'Idle' states

Concept Snapshot

UART Transmitter Module:
- Idle state: TX line is high
- Start bit: TX line low signals start
- Send 8 data bits LSB first
- Stop bit: TX line high signals end
- Returns to idle, ready for next byte

Full Transcript

This UART transmitter module starts in idle with the TX line high. When tx_start is asserted, it sends a start bit by pulling TX low. Then it sends each data bit from least significant to most significant bit, changing the TX line accordingly. After all 8 bits, it sends a stop bit by setting TX high again. Finally, it returns to idle state waiting for the next transmission. Variables like state, bit_index, and tx line value change step by step as shown in the execution table and variable tracker. This flow ensures serial data is sent correctly over UART.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily