Synthesizable vs non-synthesizable constructs in Verilog

Introduction

We use synthesizable constructs to create hardware circuits from code. Non-synthesizable constructs help us test and simulate designs but cannot become hardware.

When writing code that will become real hardware, like a chip or FPGA design.

When creating testbenches to check if hardware design works correctly.

When simulating behavior that cannot be built in hardware, like delays or file reading.

When debugging hardware designs using simulation tools.

When modeling hardware behavior before actual hardware is made.

Syntax

Verilog

// Synthesizable example
always @(posedge clk) begin
  q <= d;
end

// Non-synthesizable example
initial begin
  $display("Hello, simulation!");
  #10 $finish;
end

Synthesizable code describes hardware circuits and uses constructs like always blocks triggered by signals.

Non-synthesizable code often uses initial blocks and system tasks like $display for simulation only.

Examples

This is synthesizable code that copies input d to output q on clock's rising edge.

Verilog

always @(posedge clk) begin
  q <= d;
end

This is non-synthesizable code used only in simulation to print a message and stop after 5 time units.

Verilog

initial begin
  $display("Start simulation");
  #5 $finish;
end

Continuous assignment is synthesizable and creates hardware logic for AND operation.

Verilog

assign y = a & b;

Synthesizable code for a simple counter with reset.

Verilog

always @(posedge clk) begin
  if (reset) q <= 0;
  else q <= q + 1;
end

Sample Program

This module shows synthesizable code for a flip-flop and non-synthesizable code to print a message and stop simulation.

Verilog

`timescale 1ns/1ps
module example(input clk, input reset, input d, output reg q);

  // Synthesizable: flip-flop behavior
  always @(posedge clk) begin
    if (reset) q <= 0;
    else q <= d;
  end

  // Non-synthesizable: simulation message
  initial begin
    $display("Simulation started");
    #20 $finish;
  end

endmodule

Important Notes

Only synthesizable constructs can be turned into real hardware by synthesis tools.

Non-synthesizable constructs are useful for testing and debugging but are ignored by synthesis.

Common non-synthesizable features include initial blocks, delays (#), and system tasks like $display.

Summary

Synthesizable constructs describe hardware and run on real devices.

Non-synthesizable constructs help simulate and test designs but do not become hardware.

Use synthesizable code for design, non-synthesizable code for simulation and debugging.

Practice

1. Which of the following Verilog constructs is non-synthesizable and used only for simulation?

easy

A. Module instantiations

B. Initial blocks (initial)

C. Continuous assignments (assign)

D. Always blocks (always)

Solution

1. Step 1: Understand the role of initial blocks

   initial blocks run once at simulation start and are not synthesizable into hardware.

2. Step 2: Compare with synthesizable constructs

   always blocks, assign statements, and module instantiations describe hardware and are synthesizable.

3. Final Answer:

   Initial blocks (initial) -> Option B

4. Quick Check:

   initial = Non-synthesizable [OK]

Hint: Remember: initial blocks only simulate, never synthesize [OK]

Common Mistakes:

• Confusing always with initial
• Thinking assign is non-synthesizable
• Assuming module instantiations are simulation-only

2. Which of the following is the correct syntax for a synthesizable always block sensitive to the positive edge of clock clk?

easy

A. always @(clk or reset) begin ... end

B. always @(clk) begin ... end

C. always @(negedge clk or posedge reset) begin ... end

D. always @(posedge clk) begin ... end

Solution

1. Step 1: Identify correct edge sensitivity

   Synthesizable clocked logic uses posedge clk or negedge clk to trigger on clock edges.

2. Step 2: Check syntax correctness

   always @(posedge clk) is correct; always @(clk) triggers on any change, which is not typical for clocked logic.

3. Final Answer:

   always @(posedge clk) begin ... end -> Option D

4. Quick Check:

   Use posedge clk for clock edge sensitivity [OK]

Hint: Use posedge or negedge for clock edges [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Mixing clock and reset signals incorrectly
• Omitting begin and end for multiple statements

3. What will be the output of the following Verilog code snippet during simulation?

reg [3:0] count;
initial begin
  count = 0;
  #5 count = 4'b1010;
end
always @(posedge clk) begin
  count <= count + 1;
end

Assuming clk toggles every 1 time unit starting at 0.

medium

A. Count stays 0 until time 5, then becomes 10 and increments every clock cycle

B. Count increments every clock cycle starting from 0, then changes to 10 at time 5

C. Count increments every clock cycle starting from 0, ignoring the initial block

D. Count remains 0 throughout simulation

Solution

1. Step 1: Analyze initial block effect

   The initial block sets count to 0 at time 0, then to 10 at time 5 (delay #5).

2. Step 2: Analyze always block behavior

   The always block increments count on every positive clock edge, but the non-blocking assignment means the update happens after the clock edge, so the delayed assignment at time 5 overrides the count value at that time.

3. Final Answer:

   Count stays 0 until time 5, then becomes 10 and increments every clock cycle -> Option A

4. Quick Check:

   initial #delay executes after clock edges [OK]

Hint: Delayed initial affects count after clock increments [OK]

Common Mistakes:

• Ignoring the initial block's delayed assignment
• Assuming count increments from 10 immediately
• Confusing blocking and non-blocking assignments

4. Identify the error in the following Verilog code snippet that prevents synthesis:

always @(posedge clk) begin
  integer i;
  for (i = 0; i < 4; i = i + 1) begin
    data[i] = i;
  end
end

medium

A. Using an integer variable inside an always block for synthesis

B. Declaring a loop variable inside the always block

C. Using blocking assignment (=) instead of non-blocking (<=) inside always block

D. Using a for loop inside an always block is not synthesizable

Solution

1. Step 1: Check variable declarations and loop usage

   Declaring integer i inside the always block is allowed for synthesis as loop variable.

2. Step 2: Identify assignment type issue

   Using blocking assignment = inside clocked always block causes unintended behavior; non-blocking <= is required for registers.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) inside always block -> Option C

4. Quick Check:

   Use non-blocking (<=) in clocked always blocks [OK]

Hint: Use <= for registers inside clocked always blocks [OK]

Common Mistakes:

• Thinking loop variables cannot be declared inside always blocks
• Believing for loops are non-synthesizable
• Ignoring difference between blocking and non-blocking assignments

5. You want to create a synthesizable Verilog module that counts the number of times an input signal sig is high during clock cycles, but also print the count value for debugging during simulation. Which approach correctly separates synthesizable and non-synthesizable constructs?

hard

A. Use an always @(posedge clk) block to increment count and an initial block with $display to print count

B. Use an always @(posedge clk) block to increment count and a separate always block with $display to print count

C. Use a continuous assignment to increment count and initial block to print count

D. Use a task to increment count and a function to print count

Solution

1. Step 1: Identify synthesizable counting logic

   Counting on clock edges must be in an always @(posedge clk) block using non-blocking assignments.

2. Step 2: Identify non-synthesizable debugging code

   Printing with $display is simulation-only and must be placed in an initial or separate simulation-only block.

3. Final Answer:

   Use an always @(posedge clk) block to increment count and an initial block with $display to print count -> Option A

4. Quick Check:

   Separate hardware logic and simulation prints [OK]

Hint: Put printing in initial, counting in clocked always [OK]

Common Mistakes:

• Trying to print inside synthesizable always block
• Using continuous assignment for counting
• Confusing tasks/functions for simulation prints