Metastability and synchronizer design in Verilog

Introduction

Metastability happens when a signal changes near a clock edge and the circuit can't decide if it's a 0 or 1. Synchronizers help avoid errors by giving the signal time to settle before using it.

When receiving signals from a different clock domain.

When reading asynchronous inputs like buttons or switches.

When connecting two parts of a circuit running at different speeds.

When you want to avoid unpredictable behavior in digital circuits.

Syntax

Verilog

module synchronizer(
    input wire async_signal,
    input wire clk,
    output reg sync_signal
);

    reg sync_stage1;

    always @(posedge clk) begin
        sync_stage1 <= async_signal;
        sync_signal <= sync_stage1;
    end

endmodule

This example uses two flip-flops in series to reduce metastability risk.

The signal passes through two stages before being considered stable.

Examples

Basic 2-stage synchronizer to safely bring an asynchronous signal into the clock domain.

Verilog

module simple_sync(
    input wire async_in,
    input wire clk,
    output reg sync_out
);

    reg stage1;

    always @(posedge clk) begin
        stage1 <= async_in;
        sync_out <= stage1;
    end

endmodule

Adding a third stage can further reduce the chance of metastability.

Verilog

module three_stage_sync(
    input wire async_in,
    input wire clk,
    output reg sync_out
);

    reg stage1, stage2;

    always @(posedge clk) begin
        stage1 <= async_in;
        stage2 <= stage1;
        sync_out <= stage2;
    end

endmodule

Sample Program

This testbench shows how an asynchronous signal is synchronized to the clock using a 2-stage synchronizer. The monitor prints the signals over time.

Verilog

module testbench;
    reg async_signal;
    reg clk;
    wire sync_signal;

    synchronizer uut(
        .async_signal(async_signal),
        .clk(clk),
        .sync_signal(sync_signal)
    );

    initial begin
        clk = 0;
        async_signal = 0;
        #5 async_signal = 1; // Change async signal asynchronously
        #100 $finish;
    end

    always #5 clk = ~clk; // 10 time units clock period

    initial begin
        $monitor($time, " ns: async_signal=%b, sync_signal=%b", async_signal, sync_signal);
    end
endmodule

module synchronizer(
    input wire async_signal,
    input wire clk,
    output reg sync_signal
);

    reg sync_stage1;

    always @(posedge clk) begin
        sync_stage1 <= async_signal;
        sync_signal <= sync_stage1;
    end

endmodule

Important Notes

Metastability can't be completely eliminated but can be made very unlikely with synchronizers.

Using more stages in the synchronizer reduces risk but adds delay.

Always synchronize signals crossing clock domains to avoid errors.

Summary

Metastability happens when signals change near clock edges and cause uncertainty.

Synchronizers use multiple flip-flops to give signals time to settle.

Use synchronizers when signals come from different clocks or asynchronous sources.

Practice

1. What is the main purpose of a synchronizer in Verilog designs?

easy

A. To generate reset signals for flip-flops

B. To reduce metastability by allowing signals to settle before use

C. To convert analog signals to digital

D. To increase clock frequency for faster operation

Solution

1. Step 1: Understand metastability

   Metastability occurs when signals change close to clock edges, causing uncertain outputs.

2. Step 2: Role of synchronizers

   Synchronizers use multiple flip-flops in series to give signals time to stabilize and avoid metastability effects.

3. Final Answer:

   To reduce metastability by allowing signals to settle before use -> Option B

4. Quick Check:

   Synchronizer purpose = reduce metastability [OK]

Hint: Synchronizers help signals settle before use to avoid errors [OK]

Common Mistakes:

• Thinking synchronizers speed up clocks
• Confusing synchronizers with reset generators
• Assuming synchronizers convert signal types

2. Which Verilog code snippet correctly implements a 2-stage synchronizer for an asynchronous input async_in?

easy

A. reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end

B. reg sync1; always @(negedge clk) sync1 <= async_in;

C. wire sync1 = async_in; wire sync2 = sync1;

D. reg sync1, sync2; always @(posedge clk) begin sync2 <= async_in; sync1 <= sync2; end

Solution

1. Step 1: Identify correct synchronizer structure

   A 2-stage synchronizer uses two flip-flops in series clocked by the same clock.

2. Step 2: Check code correctness

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end correctly assigns sync1 first, then sync2 on the clock's rising edge, matching the synchronizer design.

3. Final Answer:

   reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end -> Option A

4. Quick Check:

   Two flip-flops in series = reg sync1, sync2; always @(posedge clk) begin sync1 <= async_in; sync2 <= sync1; end [OK]

Hint: Synchronizer uses two flip-flops clocked on posedge [OK]

Common Mistakes:

• Using negedge clock instead of posedge
• Assigning signals in wrong order
• Using wires instead of regs for flip-flops

3. Given the following Verilog code, what is the output value of sync_out after two clock cycles if async_in changes from 0 to 1 just before the first clock edge?

reg sync1, sync2;
always @(posedge clk) begin
  sync1 <= async_in;
  sync2 <= sync1;
end
assign sync_out = sync2;

medium

A. sync_out becomes 1 after two clock cycles

B. sync_out becomes 1 immediately at first clock edge

C. sync_out remains 0 indefinitely

D. sync_out toggles between 0 and 1 every clock

Solution

1. Step 1: Trace signal through synchronizer stages

   At first clock edge, sync1 captures async_in=1, but sync2 still holds old sync1 value (0).

2. Step 2: After second clock edge

   At second clock edge, sync2 captures sync1=1, so sync_out becomes 1.

3. Final Answer:

   sync_out becomes 1 after two clock cycles -> Option A

4. Quick Check:

   Two flip-flop delay = output after two clocks [OK]

Hint: Synchronizer output updates after two clock cycles [OK]

Common Mistakes:

• Assuming output changes immediately
• Ignoring flip-flop delay stages
• Confusing sync1 and sync2 roles

4. Identify the error in this synchronizer code snippet:

reg sync1, sync2;
always @(posedge clk) begin
  sync2 <= async_in;
  sync1 <= sync2;
end

medium

A. Clock edge should be negedge instead of posedge

B. Missing asynchronous reset signal

C. Using blocking assignments instead of non-blocking

D. The flip-flop assignments are reversed; sync1 should capture async_in first

Solution

1. Step 1: Analyze assignment order

   The first flip-flop should capture async_in, then the second captures the first flip-flop's output.

2. Step 2: Identify reversed assignments

   Here, sync2 captures async_in first, which is incorrect; sync1 should capture async_in first.

3. Final Answer:

   The flip-flop assignments are reversed; sync1 should capture async_in first -> Option D

4. Quick Check:

   Correct order: sync1 <= async_in; sync2 <= sync1 [OK]

Hint: First flip-flop captures async input, second captures first flip-flop [OK]

Common Mistakes:

• Swapping flip-flop assignment order
• Forgetting non-blocking assignments
• Assuming reset is mandatory for synchronizers

5. You need to design a synchronizer for a signal coming from a different clock domain that toggles very fast. Which approach best reduces metastability risk and ensures stable output?

hard

A. Use combinational logic to directly sample the asynchronous signal

B. Use a single flip-flop synchronizer with asynchronous reset

C. Use a 3-stage synchronizer with flip-flops clocked by the receiving clock

D. Use a 2-stage synchronizer clocked by the source clock

Solution

1. Step 1: Understand metastability risk with fast toggling signals

   Fast toggling signals crossing clock domains increase metastability risk; more synchronization stages help reduce it.

2. Step 2: Choose proper synchronizer design

   A 3-stage synchronizer clocked by the receiving clock provides more settling time and reduces metastability better than fewer stages or wrong clock domains.

3. Final Answer:

   Use a 3-stage synchronizer with flip-flops clocked by the receiving clock -> Option C

4. Quick Check:

   More stages + receiving clock = better metastability reduction [OK]

Hint: More flip-flop stages reduce metastability risk [OK]

Common Mistakes:

• Using source clock instead of receiving clock
• Using too few synchronizer stages
• Sampling asynchronously with combinational logic