Synthesis warnings and how to fix them in Verilog

Introduction

Synthesis warnings tell you about possible problems in your Verilog code before making hardware. Fixing them helps your design work correctly and efficiently.

When your FPGA or ASIC tool shows messages after compiling your Verilog code.

When your design behaves strangely or does not work as expected.

When you want to make sure your hardware uses resources well and runs fast.

When you add new code and want to check it is safe and correct.

When you want to avoid bugs that are hard to find later in hardware.

Syntax

Verilog

// No specific syntax for warnings, but common causes include:
// - Unused signals
// - Incomplete case statements
// - Latches inferred unintentionally
// - Conflicting assignments
// - Unsupported constructs

// Example of incomplete case statement causing warning:
case(sel)
  2'b00: out = a;
  2'b01: out = b;
  // Missing other cases
endcase

Synthesis warnings are messages from your synthesis tool, not Verilog code itself.

Reading and understanding these warnings helps you improve your design.

Examples

Unused signals waste hardware and cause warnings. Remove or use them.

Verilog

// Warning: Unused signal
wire unused_signal;

// Fix: Remove unused_signal or use it in code

Adding a default case prevents unintended latches and clears warnings.

Verilog

// Warning: Incomplete case statement
always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    // Missing default case
  endcase
end

// Fix: Add default case
always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    default: out = 0;
  endcase
end

Always assign outputs in all conditions to avoid latches.

Verilog

// Warning: Latch inferred
always @(posedge clk) begin
  if(enable)
    q <= d;
  // Missing else branch
end

// Fix: Add else branch
always @(posedge clk) begin
  if(enable)
    q <= d;
  else
    q <= q;
end

Sample Program

This example shows a case statement with a default case to avoid synthesis warnings about incomplete cases.

Verilog

module example(input wire clk, input wire [1:0] sel, input wire a, input wire b, output reg out);

  always @(*) begin
    case(sel)
      2'b00: out = a;
      2'b01: out = b;
      default: out = 0; // Fix: added default to avoid warning
    endcase
  end

endmodule

Important Notes

Always read synthesis warnings carefully; they guide you to fix potential design issues.

Fixing warnings early saves time and prevents hardware bugs.

Use default cases in case statements and assign all outputs in all conditions.

Summary

Synthesis warnings help find problems in your Verilog code before hardware creation.

Common causes include unused signals, incomplete cases, and missing assignments.

Fix warnings by cleaning code, adding default cases, and ensuring all outputs are assigned.

Practice

1. What is the main reason synthesis tools generate warnings about incomplete case statements in Verilog?

easy

A. Because the case statement is inside an always block.

B. Because the syntax of the case statement is incorrect.

C. Because the tool does not support case statements.

D. Because not all possible input cases are covered, which may cause unintended hardware behavior.

Solution

1. Step 1: Understand synthesis warnings for case statements

   Synthesis tools warn when a case statement does not cover all possible input values, which can cause unintended latches or hardware behavior.

2. Step 2: Reason why incomplete coverage is problematic

   If some input values are not handled, the hardware may hold previous values or behave unpredictably, which is why the tool warns.

3. Final Answer:

   Because not all possible input cases are covered, which may cause unintended hardware behavior. -> Option D

4. Quick Check:

   Incomplete case coverage = synthesis warning [OK]

Hint: Always cover all input cases in case to avoid warnings [OK]

Common Mistakes:

• Thinking syntax errors cause incomplete case warnings
• Ignoring default cases in case statements
• Assuming tools don't check for all input values

2. Which of the following Verilog code snippets will NOT cause a synthesis warning about unassigned signals?

easy

A. module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule

B. module example(input clk, input a, output reg q); always @(posedge clk) ; endmodule

C. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) temp <= a; endmodule

D. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) q <= temp; endmodule

Solution

1. Step 1: Identify unassigned signals in each snippet

   module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule assigns q on clock edge, so no unassigned output. module example(input clk, input a, output reg q); always @(posedge clk) ; endmodule has an empty always block, so q is never assigned. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) temp <= a; endmodule assigns temp but q is unassigned output. module example(input clk, input a, output reg q); reg temp; always @(posedge clk) q <= temp; endmodule assigns q from temp, but temp is never assigned.

2. Step 2: Determine which code avoids unassigned signals

   Only module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule properly assigns the output q and has no unassigned signals, so no synthesis warning.

3. Final Answer:

   module example(input clk, input a, output reg q); always @(posedge clk) q <= a; endmodule -> Option A

4. Quick Check:

   All outputs assigned = no warnings [OK]

Hint: Check if all outputs get assigned in every clock cycle [OK]

Common Mistakes:

• Ignoring that outputs must be assigned to avoid warnings
• Assuming internal regs cause warnings if unassigned
• Confusing blocking and non-blocking assignments

3. Given the following Verilog code, what synthesis warning will most likely appear?

module test(input wire [1:0] sel, output reg out);
  always @(*) begin
    case(sel)
      2'b00: out = 1'b0;
      2'b01: out = 1'b1;
      // Missing cases for 2'b10 and 2'b11
    endcase
  end
endmodule

medium

A. Warning about incomplete case statement causing inferred latch.

B. Warning about unused input sel.

C. Warning about multiple drivers for out.

D. No warnings; code is synthesizable as is.

Solution

1. Step 1: Analyze the case statement coverage

   The case covers only 2 of 4 possible values of sel. Missing 2'b10 and 2'b11 cases.

2. Step 2: Understand synthesis implications of missing cases

   Because not all cases are covered and no default is provided, synthesis infers a latch to hold out value for missing cases, causing a warning.

3. Final Answer:

   Warning about incomplete case statement causing inferred latch. -> Option A

4. Quick Check:

   Incomplete case = inferred latch warning [OK]

Hint: Add default case to avoid inferred latch warnings [OK]

Common Mistakes:

• Assuming no warning if some cases are missing
• Confusing unused input warnings with case coverage
• Ignoring latch inference from incomplete cases

4. Identify the synthesis warning and fix in the following Verilog snippet:

module fixme(input clk, input a, output reg q);
  reg temp;
  always @(posedge clk) begin
    temp <= a;
  end
  always @(posedge clk) begin
    q <= temp;
  end
endmodule

medium

A. Warning: Unused signal temp. Fix: Remove temp and assign q directly.

B. No synthesis warnings; code is correct.

C. Warning: temp is assigned but never used. Fix: Connect temp to output.

D. Warning: Multiple drivers for q. Fix: Use only one always block for q.

Solution

1. Step 1: Check signal usage and assignments

   temp is assigned from a on clock edge, then q is assigned from temp on next clock edge. Both signals are used properly.

2. Step 2: Verify if multiple drivers or unused signals exist

   Only one always block drives temp, and one drives q. No multiple drivers or unused signals.

3. Final Answer:

   No synthesis warnings; code is correct. -> Option B

4. Quick Check:

   All signals assigned and used properly = no warnings [OK]

Hint: Check if every assigned signal is used and driven once [OK]

Common Mistakes:

• Assuming temp is unused because it is intermediate
• Thinking multiple always blocks cause multiple drivers if signals differ
• Ignoring proper signal flow over clock cycles

5. You have a combinational always block with multiple outputs, but synthesis warns about inferred latches. How can you fix this warning effectively?

hard

A. Add more inputs to the sensitivity list of the always block.

B. Remove the always block and use continuous assignments instead.

C. Add a default assignment to all outputs at the start of the always block.

D. Declare all outputs as wires instead of regs.

Solution

1. Step 1: Understand why inferred latches occur in combinational blocks

   If outputs are not assigned in all possible paths, synthesis infers latches to hold previous values, causing warnings.

2. Step 2: Fix by adding default assignments

   Assign default values to all outputs at the start of the always block to ensure they are always driven, preventing latch inference.

3. Final Answer:

   Add a default assignment to all outputs at the start of the always block. -> Option C

4. Quick Check:

   Default assignments prevent inferred latches [OK]

Hint: Initialize outputs at block start to avoid latches [OK]

Common Mistakes:

• Thinking sensitivity list affects latch warnings
• Assuming changing output type fixes latch inference
• Removing always block without replacing logic