UART transmitter module in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is the main purpose of a UART transmitter module?

A UART transmitter module converts parallel data into serial data and sends it out bit by bit over a communication line.

beginner

In UART transmission, what does the 'start bit' signify?

The start bit signals the beginning of data transmission and is usually a logic low (0) to alert the receiver to start reading bits.

intermediate

How does the UART transmitter module handle the data bits during transmission?

It sends the data bits one at a time, starting from the least significant bit (LSB) to the most significant bit (MSB), after the start bit.

intermediate

What role does the baud rate generator play in a UART transmitter?

The baud rate generator controls the timing of bit transmission, ensuring bits are sent at the correct speed for the receiver to interpret correctly.

beginner

Why is a stop bit used in UART transmission?

The stop bit marks the end of the data frame and allows the receiver to recognize the frame boundary and prepare for the next data.

What is the first bit sent by a UART transmitter when sending data?

A Most significant data bit

B Stop bit

C Parity bit

D Start bit

The start bit is sent first to signal the beginning of data transmission.

In UART transmission, data bits are sent in which order?

A Least significant bit first

B Most significant bit first

C Random order

D All bits simultaneously

UART sends data bits starting from the least significant bit (LSB) first.

What does the baud rate in UART define?

A Number of data bits

B Speed of bit transmission

C Parity checking method

D Voltage level of signals

Baud rate defines how fast bits are sent over the communication line.

Which signal level usually represents the start bit in UART?

A Logic low (0)

B No signal

C Alternating 1 and 0

D Logic high (1)

The start bit is typically a logic low (0) to indicate the start of transmission.

What is the purpose of the stop bit in UART transmission?

A To start the data frame

B To check parity

C To mark the end of the data frame

D To reset the transmitter

The stop bit marks the end of the data frame so the receiver knows the frame is complete.

Explain how a UART transmitter module sends data from parallel input to serial output.

Think about the order of bits and timing control.

Describe the role of the baud rate generator in a UART transmitter module.

Consider how timing affects communication.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily