UART transmitter module in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to define the baud rate generator clock enable signal.

Verilog

assign baud_tick = (clk_count == [1]) ? 1'b1 : 1'b0;

Drag options to blanks, or click blank then click option'

Abaud_limit

Bbaud_rate

Cclk_divider

Dbit_time

Attempts:

3 left

💡 Hint

Common Mistakes

Using baud_rate instead of baud_limit causes incorrect timing.

Using clk_divider or bit_time are not defined signals here.

The baud_tick signal is asserted when the clock counter reaches the baud_limit value.

2fill in blank

medium

Complete the code to load the data into the shift register when start signal is asserted.

Verilog

if (start) shift_reg <= [1];

Drag options to blanks, or click blank then click option'

Ashift_reg

Bdata_out

Cdata_in

D1'b0

Attempts:

3 left

💡 Hint

Common Mistakes

Loading shift_reg instead of data_in causes no new data to load.

Using 1'b0 clears the register instead of loading data.

The shift register must load the input data when transmission starts.

3fill in blank

hard

Fix the error in the always block sensitivity list for synchronous logic.

Verilog

always @(posedge clk or [1]) begin

Drag options to blanks, or click blank then click option'

Anegedge reset_n

Bposedge start

Cnegedge clk

Dposedge reset_n

Attempts:

3 left

💡 Hint

Common Mistakes

Using posedge reset_n causes reset to trigger incorrectly.

Using posedge start or negedge clk are not standard for reset.

The asynchronous reset is usually active low and triggered on the negative edge.

4fill in blank

hard

Fill both blanks to correctly shift the data and update the bit counter.

Verilog

if (baud_tick) begin
  shift_reg <= shift_reg[1] 1;
  bit_count <= bit_count [2] 1;
end

Drag options to blanks, or click blank then click option'

A<<

B+

C-

D>>

Attempts:

3 left

💡 Hint

Common Mistakes

Shifting left (<<) would send MSB first, which is incorrect here.

Decrementing bit_count causes wrong bit tracking.

The shift register shifts right to send LSB first, and bit_count increments by 1.

5fill in blank

hard

Fill all three blanks to define the UART transmitter output logic with start, data, and stop bits.

Verilog

assign tx = (state == [1]) ? 1'b0 :
             (state == [2]) ? shift_reg[0] :
             (state == [3]) ? 1'b1 : 1'b1;

Drag options to blanks, or click blank then click option'

ASTART_BIT

BDATA_BITS

CSTOP_BIT

DIDLE

Attempts:

3 left

💡 Hint

Common Mistakes

Mixing up start and stop bit states causes wrong output levels.

Using IDLE state for data bits is incorrect.

The transmitter outputs 0 during start bit, data bits from shift_reg, and 1 during stop bit.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily