UART transmitter module in Verilog

Introduction

A UART transmitter module sends data one bit at a time over a wire. It helps two devices talk to each other using serial communication.

When you want to send text from a microcontroller to a computer.

When connecting sensors that send data serially to a processor.

When debugging embedded systems by sending messages over UART.

When building communication between two chips using serial data.

When you need a simple way to send data without many wires.

Syntax

Verilog

module uart_tx(
    input wire clk,
    input wire reset,
    input wire tx_start,
    input wire [7:0] tx_data,
    output reg tx,
    output reg tx_busy
);

// UART transmitter logic here

endmodule

clk is the clock signal to time the data sending.

tx_start tells the module to start sending data.

Examples

This is the basic structure of a UART transmitter module with inputs and outputs.

Verilog

module uart_tx(
    input wire clk,
    input wire reset,
    input wire tx_start,
    input wire [7:0] tx_data,
    output reg tx,
    output reg tx_busy
);

// Simple UART transmitter logic

endmodule

This shows how to start sending data on a clock edge and reset the transmitter.

Verilog

always @(posedge clk or posedge reset) begin
    if (reset) begin
        tx <= 1'b1; // Idle state is high
        tx_busy <= 0;
    end else if (tx_start) begin
        // Start sending data bits here
    end
end

Sample Program

This UART transmitter module sends 8 bits of data with a start bit and a stop bit. It uses a clock to time each bit. When tx_start is high, it begins sending tx_data serially on tx. The tx_busy signal shows when it is sending.

Verilog

module uart_tx(
    input wire clk,
    input wire reset,
    input wire tx_start,
    input wire [7:0] tx_data,
    output reg tx,
    output reg tx_busy
);

    parameter CLKS_PER_BIT = 87; // For 115200 baud with 10 MHz clock

    reg [7:0] tx_shift_reg = 8'b0;
    reg [6:0] clk_count = 0;
    reg [3:0] bit_index = 0;
    reg sending = 0;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            tx <= 1'b1; // Idle line is high
            tx_busy <= 0;
            clk_count <= 0;
            bit_index <= 0;
            sending <= 0;
            tx_shift_reg <= 8'b0;
        end else begin
            if (tx_start && !sending) begin
                sending <= 1;
                tx_busy <= 1;
                tx_shift_reg <= tx_data;
                clk_count <= 0;
                bit_index <= 0;
                tx <= 0; // Start bit
            end else if (sending) begin
                if (clk_count < CLKS_PER_BIT - 1) begin
                    clk_count <= clk_count + 1;
                end else begin
                    clk_count <= 0;
                    bit_index <= bit_index + 1;
                    if (bit_index < 8) begin
                        tx <= tx_shift_reg[0];
                        tx_shift_reg <= tx_shift_reg >> 1;
                    end else if (bit_index == 8) begin
                        tx <= 1; // Stop bit
                    end else begin
                        tx <= 1; // Idle
                        sending <= 0;
                        tx_busy <= 0;
                    end
                end
            end else begin
                tx <= 1; // Idle
                tx_busy <= 0;
            end
        end
    end

endmodule

Important Notes

The UART line is usually high when idle.

The start bit is low to signal the beginning of data.

The stop bit is high to signal the end of data.

Summary

A UART transmitter sends data bit by bit over one wire.

It uses start and stop bits to mark data boundaries.

It needs a clock to time each bit sent.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily