Code coverage concepts in Verilog

Introduction

Code coverage helps check if your Verilog test covers all parts of your design. It shows what is tested and what is missed.

When you want to know if your testbench tests every part of your design.

When you need to find untested parts in your Verilog code before finalizing.

When you want to improve your test quality by adding missing tests.

When you want to measure how much of your design is exercised by tests.

When you want to avoid bugs by ensuring all conditions and states are checked.

Syntax

Verilog

// Example of coverage block in SystemVerilog
covergroup cg;
  coverpoint signal_name {
    bins low = {0};
    bins high = {1};
  }
endgroup

initial begin
  cg cg_inst = new();
  cg_inst.sample(signal_name);
end

Verilog itself does not have built-in coverage, but SystemVerilog adds coverage features.

Coverage groups and coverpoints help track which values or states occur during simulation.

Examples

This example tracks how often different states occur.

Verilog

covergroup cg;
  coverpoint state;
endgroup

initial begin
  cg cg_inst = new();
  cg_inst.sample(state);
end

This example divides data values into bins for zero, positive, and negative ranges.

Verilog

covergroup cg;
  coverpoint data {
    bins zero = {0};
    bins positive = {[1:127]};
    bins negative = {[-128:-1]};
  }
endgroup

This example tracks specific opcode values during simulation.

Verilog

covergroup cg;
  coverpoint opcode {
    bins add = {4'b0001};
    bins sub = {4'b0010};
  }
endgroup

Sample Program

This program defines a coverage group to track the 'state' signal values. It samples three states: idle, run, and stop.

Verilog

`timescale 1ns/1ps
module coverage_example();
  reg [1:0] state;

  covergroup cg;
    coverpoint state {
      bins idle = {2'b00};
      bins run = {2'b01};
      bins stop = {2'b10};
    }
  endgroup

  cg cg_inst;

  initial begin
    cg_inst = new();
    state = 2'b00; // idle
    #10 cg_inst.sample(state);
    state = 2'b01; // run
    #10 cg_inst.sample(state);
    state = 2'b10; // stop
    #10 cg_inst.sample(state);
    $display("Coverage example finished.");
    $finish;
  end
endmodule

Important Notes

Code coverage helps find parts of your design not tested by your testbench.

SystemVerilog coverage features include covergroups, coverpoints, and bins.

Coverage data is collected during simulation and can be viewed with tools.

Summary

Code coverage shows which parts of your Verilog design are tested.

Use SystemVerilog covergroups and coverpoints to define coverage points.

Sampling coverage during simulation helps improve test quality.

Practice

1. What is the main purpose of code coverage in Verilog simulations?

easy

A. To generate synthesis reports

B. To speed up the simulation runtime

C. To check which parts of the design have been tested

D. To optimize the hardware layout

Solution

1. Step 1: Understand code coverage concept

   Code coverage tracks which parts of the Verilog design are exercised during simulation.

2. Step 2: Identify the main goal

   The goal is to ensure tests cover all design parts, improving test quality.

3. Final Answer:

   To check which parts of the design have been tested -> Option C

4. Quick Check:

   Code coverage = tested parts check [OK]

Hint: Code coverage shows tested design parts, not speed or layout [OK]

Common Mistakes:

• Confusing coverage with simulation speed
• Thinking coverage generates synthesis reports
• Assuming coverage optimizes hardware layout

2. Which SystemVerilog construct is used to define a coverage point in code coverage?

easy

A. coverpoint

B. assertion

C. covergroup

D. property

Solution

1. Step 1: Recall coverage constructs

   SystemVerilog uses covergroup to group coverage points and coverpoint to define individual coverage points.

2. Step 2: Identify the coverage point

   The coverage point is specifically defined by coverpoint, inside a covergroup.

3. Final Answer:

   coverpoint -> Option A

4. Quick Check:

   Coverage point = coverpoint [OK]

Hint: Coverpoint defines coverage points inside covergroups [OK]

Common Mistakes:

• Confusing covergroup with coverpoint
• Using assertion or property for coverage points
• Mixing coverage with verification constructs

3. Given the following code snippet, what will be the coverage count for state after these values: 0, 1, 0, 2?

int state;
covergroup cg;
  coverpoint state;
endgroup

cg cg_inst = new();
state = 0;
cg_inst.sample();
state = 1;
cg_inst.sample();
state = 0;
cg_inst.sample();
state = 2;
cg_inst.sample();

medium

A. 1

B. 4

C. 2

D. 3

Solution

1. Step 1: Understand coverage counting

   Coverage counts unique values sampled by the coverpoint. Values 0,1,2 appear.

2. Step 2: Count unique values

   Values sampled: 0 (twice), 1, 2. Unique values are 0,1,2 -> 3 unique hits.

3. Final Answer:

   3 -> Option D

4. Quick Check:

   Unique states = 3 [OK]

Hint: Count unique sampled values for coverage count [OK]

Common Mistakes:

• Counting repeated samples multiple times
• Assuming total samples equal coverage count
• Ignoring unique value concept

4. Identify the error in this coverage code snippet:

int signal;
covergroup cg;
  coverpoint signal {
    bins low = {0};
    bins high = {1};
  }
endgroup

cg cg_inst = new();
signal = 2;
cg_inst.sample();

medium

A. Missing semicolon after coverpoint declaration

B. Bins do not cover the sampled value 2

C. covergroup must have a constructor

D. sample() method is not valid

Solution

1. Step 1: Analyze bins coverage

   Bins cover values 0 and 1 only. Sampled value is 2, which is not covered.

2. Step 2: Identify error impact

   Sampling 2 will not hit any bin, causing incomplete coverage.

3. Final Answer:

   Bins do not cover the sampled value 2 -> Option B

4. Quick Check:

   Bins coverage missing sampled value [OK]

Hint: Check if bins cover all sampled values [OK]

Common Mistakes:

• Ignoring uncovered sampled values
• Thinking semicolon is missing after coverpoint
• Assuming sample() method is invalid

5. How can you combine multiple coverpoints in a covergroup to track cross coverage of signals a and b in SystemVerilog?

hard

A. Define coverpoints for a and b and add a cross coverage for both inside the covergroup

B. Define separate covergroups for a and b without cross coverage

C. Use assertions to check a and b values

D. Sample a and b separately without grouping

Solution

1. Step 1: Understand covergroup composition

   A covergroup can contain multiple coverpoints to track individual signals.

2. Step 2: Use cross coverage

   Cross coverage tracks combinations of values from multiple coverpoints, here a and b.

3. Final Answer:

   Define coverpoints for a and b and add a cross coverage for both inside the covergroup -> Option A

4. Quick Check:

   Cross coverage = combined signal tracking [OK]

Hint: Use cross coverage inside covergroup for multiple signals [OK]

Common Mistakes:

• Not using cross coverage for combined signals
• Defining separate covergroups without cross
• Confusing assertions with coverage