UART transmitter module in Verilog - Deep Dive

Overview - UART transmitter module

What is it?

A UART transmitter module is a hardware design that sends data serially using the Universal Asynchronous Receiver/Transmitter (UART) protocol. It converts parallel data from a system into a serial stream of bits, adding start, stop, and optional parity bits for communication. This module is often written in Verilog to be implemented on FPGAs or ASICs. It enables devices to communicate over serial lines without a clock signal shared between sender and receiver.

Why it matters

Without a UART transmitter, devices would struggle to send data over simple serial connections reliably. UART allows asynchronous communication, meaning devices don't need to share a clock, making wiring simpler and cheaper. This is crucial in embedded systems, sensors, and computers where serial communication is common. Without UART transmitters, data transfer would be slower, more complex, or require more hardware.

Where it fits

Before learning UART transmitters, you should understand basic digital logic, binary data, and Verilog syntax. After mastering UART transmitters, you can learn UART receivers, full UART communication systems, and advanced serial protocols like SPI or I2C.

Mental Model

Core Idea

A UART transmitter takes parallel data and sends it out one bit at a time with start and stop signals to mark the data boundaries, enabling asynchronous serial communication.

Think of it like...

It's like sending a message in a bottle down a river where you add a special flag at the start and end of the message so the receiver knows when the message begins and ends, even if they don't know exactly when you sent it.

┌───────────────┐
│ Parallel Data │
└──────┬────────┘
       │
       ▼
┌─────────────────────┐
│ UART Transmitter     │
│ - Adds start bit     │
│ - Sends bits serially│
│ - Adds stop bit      │
└─────────┬───────────┘
          │
          ▼
   Serial Data Out →─────>

Build-Up - 7 Steps

1

Foundation

Understanding UART Basics

Concept: Introduce the UART protocol and its key components: start bit, data bits, parity bit, and stop bit.

UART sends data serially without a shared clock. Each data packet starts with a start bit (logic 0), followed by data bits (usually 8), optional parity bit for error checking, and one or two stop bits (logic 1). The receiver uses these bits to know when data starts and ends.

Result

You know the structure of UART data frames and why start and stop bits are needed.

Understanding the UART frame structure is essential because the transmitter must add these bits correctly to ensure the receiver can decode the data.

2

Foundation

Verilog Basics for UART

Concept: Learn how to write simple Verilog modules and use registers and always blocks for sequential logic.

Verilog modules define hardware blocks. Registers store data, and always blocks describe behavior on clock edges. For UART, you will use these to hold data and control timing for sending bits.

Result

You can write a basic Verilog module that stores data and reacts to clock signals.

Knowing how to write sequential logic in Verilog is the foundation for building a UART transmitter that sends bits in order.

3

Intermediate

Implementing Bit Timing Control

🤔Before reading on: do you think the UART transmitter sends bits at the same speed as the system clock or a slower rate? Commit to your answer.

Concept: Introduce baud rate generation to control the timing of each bit sent over the serial line.

UART bits must be sent at a specific speed called baud rate (e.g., 9600 bits per second). Since the system clock is usually faster, a baud rate generator divides the clock to create a tick signal that tells the transmitter when to send the next bit.

Result

You can generate a timing signal that controls when each bit is transmitted.

Controlling bit timing ensures data is sent at the correct speed, matching the receiver's expectations and preventing errors.

4

Intermediate

Building the Transmit State Machine

🤔Before reading on: do you think the transmitter sends all bits at once or one after another? Commit to your answer.

Concept: Use a finite state machine (FSM) to manage the sequence of sending start bit, data bits, and stop bit.

The FSM has states like IDLE, START, DATA, and STOP. It waits for a send signal, then sends the start bit, each data bit in order, and finally the stop bit. The FSM moves to the next state on each baud tick.

Result

You have a clear control flow that sends bits in the correct order.

Using an FSM organizes the transmission process, making the design reliable and easier to debug.

5

Intermediate

Loading and Shifting Data Bits

Concept: Learn how to load parallel data and shift it out bit by bit serially.

When transmission starts, the parallel data byte is loaded into a shift register. On each baud tick, the least significant bit is sent out, and the register shifts right to prepare the next bit.

Result

Data is sent serially, one bit at a time, from the loaded byte.

Shifting data out bit by bit is the core mechanism that converts parallel data into serial form.

6

Advanced

Handling Transmission Completion and Ready Signals

🤔Before reading on: do you think the transmitter can accept new data while sending current data? Commit to your answer.

Concept: Manage signals that indicate when the transmitter is busy or ready for new data.

The transmitter asserts a 'busy' signal during transmission and a 'ready' signal when it can accept new data. This prevents data loss by ensuring new data is only loaded when the transmitter is idle.

Result

The system knows when to send new data safely without overwriting ongoing transmission.

Proper handshaking signals prevent data corruption and enable smooth communication with other system parts.

7

Expert

Optimizing for Clock Domain and Glitch Avoidance

🤔Before reading on: do you think glitches can occur if signals change asynchronously? Commit to your answer.

Concept: Understand how to synchronize signals and avoid glitches in asynchronous serial communication.

Since UART is asynchronous, the transmitter clock and system clock may differ. Using proper synchronization techniques and glitch-free signal assignments ensures reliable data transmission without timing errors or metastability.

Result

The transmitter works reliably even when clocks are not perfectly aligned.

Knowing how to handle clock domains and signal integrity is crucial for robust UART transmitter designs in real hardware.

Under the Hood

Internally, the UART transmitter uses a clock divider to generate a baud rate tick from the system clock. A finite state machine controls the sending process, moving through states to send start bit, data bits, and stop bit. A shift register holds the data byte and shifts it out bit by bit on each baud tick. Control signals manage when new data can be loaded. The output line is driven by the current bit being sent, ensuring the serial data stream follows UART protocol timing.

Why designed this way?

UART was designed for simple, low-cost asynchronous serial communication without needing a shared clock line. The start and stop bits frame the data so receivers can synchronize on each byte. Using a shift register and FSM in hardware allows precise control of timing and bit order. This design balances simplicity, reliability, and hardware resource use, making UART widely adopted in embedded systems.

┌───────────────┐
│ System Clock  │
└──────┬────────┘
       │
       ▼
┌───────────────┐      ┌───────────────┐      ┌───────────────┐
│ Baud Rate     │─────▶│ FSM Controller│─────▶│ Shift Register│
│ Generator     │      │ (States)      │      │ (Data bits)   │
└───────────────┘      └──────┬────────┘      └──────┬────────┘
                                │                     │
                                ▼                     ▼
                          ┌───────────────┐     ┌───────────────┐
                          │ Output Logic  │────▶│ Serial TX Pin │
                          └───────────────┘     └───────────────┘

Myth Busters - 4 Common Misconceptions

Quick: Does UART require a shared clock signal between sender and receiver? Commit to yes or no.

Common Belief: UART communication needs both devices to share the same clock signal to stay synchronized.

Reality: UART is asynchronous and does not require a shared clock; it uses start and stop bits to synchronize each byte.

Why it matters: Believing a shared clock is needed can lead to overcomplicated designs and misunderstanding of UART's simplicity and flexibility.

Quick: Do you think the UART transmitter sends data bits in parallel or serially? Commit to your answer.

Common Belief: The UART transmitter sends all data bits at once in parallel.

Reality: The UART transmitter sends data bits one at a time, serially, over a single wire.

Why it matters: Misunderstanding this causes confusion about how UART reduces wiring complexity and why timing control is critical.

Quick: Can the UART transmitter accept new data while still sending the previous byte? Commit to yes or no.

Common Belief: The transmitter can load new data anytime, even during ongoing transmission.

Reality: The transmitter must finish sending the current byte before accepting new data to avoid data corruption.

Why it matters: Ignoring this leads to lost or corrupted data and unreliable communication.

Quick: Is the stop bit always a logic 0? Commit to yes or no.

Common Belief: The stop bit is a logic 0, just like the start bit.

Reality: The stop bit is a logic 1, marking the line idle state after data transmission.

Why it matters: Confusing stop bit polarity breaks communication because receivers expect a high line to detect the end of a byte.

Expert Zone

1

The exact timing of baud rate ticks must consider clock frequency and rounding errors to avoid drift over long transmissions.

2

Some UART transmitters support configurable parity bits and multiple stop bits, requiring flexible FSM design.

3

Glitches on the serial output line can cause framing errors; careful signal assignment and synchronization are needed to prevent this.

When NOT to use

UART transmitters are not suitable for high-speed or multi-device bus communication. For those cases, protocols like SPI or I2C are better. Also, if clock synchronization is available, synchronous serial protocols may be more efficient.

Production Patterns

In real systems, UART transmitters often include FIFOs to buffer multiple bytes, support for flow control signals (RTS/CTS), and error detection. They are integrated with interrupt controllers to notify the CPU when transmission completes.

Connections

Finite State Machines (FSM)

UART transmitter control uses FSMs to sequence bit transmission states.

Understanding FSMs helps grasp how UART transmitters manage complex timing and control flows in hardware.

Shift Registers

UART transmitters use shift registers to convert parallel data into serial bits.

Knowing shift registers clarifies how data is serialized efficiently in hardware.

Human Speech Communication

Both use start and stop signals to frame information for asynchronous understanding.

Recognizing that asynchronous framing exists in human speech helps appreciate why UART uses start and stop bits to synchronize data without a shared clock.

Common Pitfalls

#1 Sending data bits without adding start and stop bits.

Wrong approach:

always @(posedge clk) begin
tx_line <= data_byte[bit_index];
bit_index <= bit_index + 1;
end

Correct approach:

Use an FSM to send a start bit (0), then data bits, then stop bit (1) in sequence, triggered by baud rate ticks.

Root cause:

Misunderstanding UART frame structure leads to missing framing bits, causing receiver synchronization failure.

#2 Loading new data into the transmitter while it is still sending previous data.

Wrong approach:

if (send) begin
shift_reg <= new_data;
end

Correct approach:

Load new data only when transmitter signals ready or idle state to avoid overwriting ongoing transmission.

Root cause:

Ignoring transmitter busy status causes data corruption and loss.

#3 Using system clock directly to time bit transmission without baud rate division.

Wrong approach:

always @(posedge clk) begin
tx_line <= next_bit;
end

Correct approach:

Generate a baud rate tick by dividing the system clock and send bits only on these ticks.

Root cause:

Not controlling bit timing causes bits to be sent too fast or irregularly, breaking communication.

Key Takeaways

UART transmitters convert parallel data into serial form by adding start and stop bits to frame each byte for asynchronous communication.

Precise timing control using a baud rate generator is essential to send bits at the correct speed matching the receiver.

A finite state machine organizes the transmission process, ensuring bits are sent in the right order and timing.

Shift registers are used to serialize data bits, sending one bit per baud tick.

Proper handshaking signals prevent data loss by indicating when the transmitter is ready for new data.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily