Edge detector (rising, falling, both) in Verilog

Introduction

An edge detector helps you find when a signal changes from low to high or high to low. This is useful to react exactly at the moment a change happens.

You want to start an action when a button is pressed (signal goes from 0 to 1).

You need to detect when a sensor signal stops (signal goes from 1 to 0).

You want to count how many times a signal changes either up or down.

You want to trigger a process only once when a signal changes state.

You want to synchronize events with signal changes in digital circuits.

Syntax

Verilog

module edge_detector(
    input wire clk,
    input wire signal_in,
    output wire rising_edge,
    output wire falling_edge,
    output wire any_edge
);

reg signal_delayed;

always @(posedge clk) begin
    signal_delayed <= signal_in;
end

assign rising_edge =  signal_in & ~signal_delayed;
assign falling_edge = ~signal_in &  signal_delayed;
assign any_edge = rising_edge | falling_edge;

endmodule

The input signal is sampled on the clock's rising edge to detect changes.

We use a delayed version of the signal to compare current and previous states.

Examples

This detects when the signal changes from 0 to 1 (rising edge).

Verilog

assign rising_edge = signal_in & ~signal_delayed;

This detects when the signal changes from 1 to 0 (falling edge).

Verilog

assign falling_edge = ~signal_in & signal_delayed;

This detects any change, either rising or falling.

Verilog

assign any_edge = rising_edge | falling_edge;

Sample Program

This testbench creates a clock and changes the input signal to show how the edge detector outputs change.

Verilog

module test_edge_detector();

reg clk = 0;
reg signal_in = 0;
wire rising_edge, falling_edge, any_edge;

// Instantiate the edge detector
edge_detector uut(
    .clk(clk),
    .signal_in(signal_in),
    .rising_edge(rising_edge),
    .falling_edge(falling_edge),
    .any_edge(any_edge)
);

// Clock generation: 10 time units period
always #5 clk = ~clk;

initial begin
    $display("Time clk signal_in rising_edge falling_edge any_edge");
    $monitor("%4d   %b    %b         %b           %b          %b", $time, clk, signal_in, rising_edge, falling_edge, any_edge);

    // Wait for a few clock cycles
    #10;
    signal_in = 1; // rising edge
    #10;
    signal_in = 0; // falling edge
    #10;
    signal_in = 1; // rising edge
    #10;
    signal_in = 1; // no edge
    #10;
    signal_in = 0; // falling edge
    #10;
    $finish;
end

endmodule

Important Notes

Make sure the input signal is synchronized with the clock to avoid glitches.

The edge detector only works correctly if the clock is fast enough to catch changes.

Delaying the signal by one clock cycle helps compare current and previous states easily.

Summary

Edge detectors find when signals change from low to high or high to low.

They use a delayed signal to compare past and current values.

Outputs can detect rising edges, falling edges, or both.

Practice

1. What does a rising edge detector in Verilog detect?
always @(posedge clk) is often used in such detectors.

easy

A. Both 0 to 1 and 1 to 0 changes

B. A change of signal from 1 to 0

C. A change of signal from 0 to 1

D. No change in signal

Solution

1. Step 1: Understand rising edge meaning

   A rising edge means the signal changes from low (0) to high (1).

2. Step 2: Relate to Verilog edge detection

   The posedge keyword triggers on this rising edge.

3. Final Answer:

   A change of signal from 0 to 1 -> Option C

4. Quick Check:

   Rising edge = 0 to 1 transition [OK]

Hint: Rising edge means signal goes from 0 to 1 [OK]

Common Mistakes:

• Confusing rising edge with falling edge
• Thinking it detects no change
• Mixing up posedge and negedge keywords

2. Which of the following Verilog code snippets correctly detects a falling edge of signal sig?

easy

A. always @(negedge sig) begin // detect falling edge end

B. always @(posedge sig) begin // detect falling edge end

C. always @(sig) begin // detect falling edge end

D. always @(posedge clk) if (sig == 1) // detect falling edge

Solution

1. Step 1: Identify falling edge keyword

   Falling edge detection uses negedge in Verilog.

2. Step 2: Match code to falling edge

   always @(negedge sig) begin // detect falling edge end uses always @(negedge sig), which triggers on signal going from 1 to 0.

3. Final Answer:

   always @(negedge sig) begin // detect falling edge end -> Option A

4. Quick Check:

   Falling edge = negedge keyword [OK]

Hint: Use negedge to detect falling edges in Verilog [OK]

Common Mistakes:

• Using posedge for falling edge detection
• Using level-sensitive sensitivity list
• Confusing signal and clock edges

3. Given this Verilog code snippet for detecting both edges of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire edge_detect = sig ^ sig_d;

What is the value of edge_detect when sig changes from 0 to 1?

medium

A. 1

B. 0

C. Undefined (X)

D. Remains previous value

Solution

1. Step 1: Understand delayed signal sig_d

   sig_d holds previous clock cycle's sig value.

2. Step 2: Calculate XOR for edge detection

   When sig changes from 0 to 1, XOR with previous 0 gives 1, indicating an edge.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   sig ^ sig_d = 1 on edge [OK]

Hint: XOR current and delayed signal to detect edges [OK]

Common Mistakes:

• Forgetting to delay signal before XOR
• Assuming edge_detect stays 0 on change
• Confusing XOR with AND or OR

4. Identify the error in this Verilog code intended to detect a rising edge of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire rising_edge = sig & ~sig_d;

medium

A. Using blocking assignment instead of non-blocking

B. Incorrect logic for rising edge detection

C. No sensitivity list for wire rising_edge

D. Missing initial value for sig_d

Solution

1. Step 1: Analyze rising edge logic

   Rising edge is when signal changes from 0 to 1, so previous was 0 and current is 1.

2. Step 2: Check given logic expression

   The expression sig & ~sig_d correctly detects rising edge by current high and previous low.

3. Step 3: Re-examine for errors

   Actually, the logic is correct; the error is elsewhere.

4. Step 4: Identify actual error

   Missing initial value for sig_d can cause unknown behavior at start.

5. Final Answer:

   Missing initial value for sig_d -> Option D

6. Quick Check:

   Initialize delayed signal to avoid unknowns [OK]

Hint: Initialize delayed signals to avoid unknown start values [OK]

Common Mistakes:

• Assuming logic expression is wrong
• Ignoring initial values for registers
• Confusing blocking and non-blocking assignments

5. You want to design a Verilog module that outputs a pulse of 1 clock cycle width whenever sig changes either from 0 to 1 or 1 to 0. Which code snippet correctly implements this?

hard

A. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig & ~sig_d;

B. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig ^ sig_d;

C. wire edge_pulse = (sig == 1) ? 1 : 0;

D. always @(posedge sig) edge_pulse = 1;

Solution

1. Step 1: Understand requirement for both edges

   The pulse should be high for one clock cycle on any signal change (rising or falling).

2. Step 2: Analyze each option

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; uses XOR between current and delayed signal, which is 1 only on change, producing a 1-cycle pulse.

3. Step 3: Confirm other options

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig & ~sig_d; detects only rising edge; C is level detection; D triggers on posedge of sig, not clock, and lacks pulse width control.

4. Final Answer:

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; -> Option B

5. Quick Check:

   XOR current and delayed signal for both edges pulse [OK]

Hint: XOR current and delayed signals for both edges pulse [OK]

Common Mistakes:

• Using only rising edge logic for both edges
• Triggering on signal edge instead of clock
• Not producing single clock cycle pulse