Port connection by name vs by position in Verilog

Introduction

Port connections link signals between modules. Connecting by name or by position helps organize and control these links clearly.

When you want to connect signals clearly and avoid mistakes in large modules.

When you add or remove ports and want to keep connections correct without changing all code.

When you want to improve readability by showing which signal connects to which port.

When you have many ports and want to avoid errors caused by wrong order.

When you want quick connections in small modules without naming each port.

Syntax

Verilog

module_name instance_name (port1, port2, port3);

// or by name
module_name instance_name (.port1(signal1), .port2(signal2), .port3(signal3));

By position: ports are connected in the order they are declared in the module.

By name: ports are connected explicitly by their names, order does not matter.

Examples

Connects ports by position: first port to 'a', second to 'b', third to 'c'.

Verilog

my_module inst1 (a, b, c);

Connects ports by name: 'port1' to 'a', 'port2' to 'b', 'port3' to 'c'. Order can be different.

Verilog

my_module inst2 (.port1(a), .port2(b), .port3(c));

By name connection allows any order of ports.

Verilog

my_module inst3 (.port3(c), .port1(a), .port2(b));

Sample Program

This example shows a simple module with two inputs and one output. It is instantiated twice: once connecting ports by position, once by name. Both produce the same output.

Verilog

module my_module(input wire in1, input wire in2, output wire out);
  assign out = in1 & in2;
endmodule

module top;
  wire a = 1'b1;
  wire b = 1'b0;
  wire c_pos, c_name;

  // Connect by position
  my_module inst_pos (a, b, c_pos);

  // Connect by name
  my_module inst_name (.in2(b), .out(c_name), .in1(a));

  initial begin
    $display("Output by position: %b", c_pos);
    $display("Output by name: %b", c_name);
  end
endmodule

Important Notes

Connecting by name is safer when module ports change order or new ports are added.

Connecting by position is shorter but can cause errors if port order is forgotten.

Use named connections for better readability and maintenance in bigger designs.

Summary

Port connection by position links signals in the order ports are declared.

Port connection by name links signals explicitly by port names, order does not matter.

Named connections improve clarity and reduce errors in complex modules.

Practice

1. What is the main difference between port connection by name and port connection by position in Verilog?

easy

A. By position allows skipping ports; by name does not allow skipping ports.

B. By position connects ports explicitly by their names; by name connects ports in the order declared.

C. By name requires fewer ports; by position requires all ports to be connected.

D. By name connects ports explicitly by their names; by position connects ports in the order declared.

Solution

1. Step 1: Understand port connection by position

   Port connection by position links signals to ports based on the order the ports are declared in the module.

2. Step 2: Understand port connection by name

   Port connection by name links signals explicitly by specifying the port names, so order does not matter.

3. Final Answer:

   By name connects ports explicitly by their names; by position connects ports in the order declared. -> Option D

4. Quick Check:

   Port connection by name = explicit naming [OK]

Hint: Remember: name = explicit, position = order [OK]

Common Mistakes:

• Confusing order with explicit naming
• Thinking by position allows skipping ports
• Assuming by name requires fewer ports

2. Which of the following is the correct syntax for connecting ports by name in Verilog?

easy

A. module_name (input_signal, output_signal);

B. module_name (.port1(input_signal), .port2(output_signal));

C. module_name {port1: input_signal, port2: output_signal};

D. module_name -> (port1=input_signal, port2=output_signal);

Solution

1. Step 1: Recall named port connection syntax

   Named connections use dot notation: .port_name(signal_name).

2. Step 2: Match syntax options

   module_name (.port1(input_signal), .port2(output_signal)); matches the correct syntax: module_name (.port1(input_signal), .port2(output_signal));

3. Final Answer:

   module_name (.port1(input_signal), .port2(output_signal)); -> Option B

4. Quick Check:

   Named ports use dot and parentheses [OK]

Hint: Named ports use dot before port name [OK]

Common Mistakes:

• Using commas without dots for named ports
• Using braces or arrows which are invalid
• Confusing named and positional syntax

3. Given the module declaration:

module my_module(input a, input b, output c);

Which instantiation will correctly connect signals x, y, and z by position?

medium

A. my_module instance1 (.a(x), .b(y), .c(z));

B. my_module instance1 (z, y, x);

C. my_module instance1 (x, y, z);

D. my_module instance1 (.c(z), .b(y), .a(x));

Solution

1. Step 1: Understand port order in module

   The ports are declared in order: a, b, c.

2. Step 2: Match signals by position

   By position, the first signal connects to 'a', second to 'b', third to 'c'. So (x, y, z) matches correctly.

3. Final Answer:

   my_module instance1 (x, y, z); -> Option C

4. Quick Check:

   Position order = a=x, b=y, c=z [OK]

Hint: Position order matches port declaration order [OK]

Common Mistakes:

• Swapping signal order in positional connection
• Using named syntax but calling it positional
• Connecting signals in wrong order

4. Identify the error in this module instantiation:

my_module instance1 (x, .b(y), z);

Assuming my_module ports are a, b, c in order.

medium

A. Mixing positional and named connections is not allowed.

B. The named connection .b(y) is correct here.

C. The order of signals is correct for positional connection.

D. No error; this is valid syntax.

Solution

1. Step 1: Check connection styles used

   The instantiation mixes positional (x, z) and named (.b(y)) connections.

2. Step 2: Recall Verilog rules on mixing connections

   Verilog does not allow mixing positional and named port connections in the same instantiation.

3. Final Answer:

   Mixing positional and named connections is not allowed. -> Option A

4. Quick Check:

   Mixing connection styles = error [OK]

Hint: Do not mix named and positional in one instantiation [OK]

Common Mistakes:

• Thinking mixed connections are allowed
• Ignoring order importance in positional connections
• Assuming named connections can appear anywhere

5. You have a module with ports declared as (input clk, input reset, output reg done). You want to instantiate it with signals clk_sig, rst_sig, and done_sig. Which instantiation style is safer and why?

hard

A. By name, because it explicitly connects signals to ports regardless of order.

B. By position, because it is shorter and easier to write.

C. By position, because it allows skipping some ports.

D. By name, because it automatically matches signals by data type.

Solution

1. Step 1: Consider risks of positional connection

   Positional connection depends on port order; if order changes, connections break.

2. Step 2: Consider benefits of named connection

   Named connection explicitly links signals to port names, so order changes do not cause errors.

3. Final Answer:

   By name, because it explicitly connects signals to ports regardless of order. -> Option A

4. Quick Check:

   Named connection = safer for clarity [OK]

Hint: Use named ports to avoid order mistakes [OK]

Common Mistakes:

• Assuming positional is always simpler and safer
• Thinking named connection matches by data type
• Believing positional allows skipping ports