UART transmitter module in Verilog - Mini Project: Build & Apply

UART transmitter module

📖 Scenario: You are designing a UART transmitter module for a simple serial communication system. UART (Universal Asynchronous Receiver/Transmitter) sends data bits one by one over a single wire. This module will take an 8-bit data input and send it out serially with start and stop bits.

🎯 Goal: Build a UART transmitter module in Verilog that sends 8-bit data serially with a start bit, 8 data bits, and a stop bit. You will create the data input, configure the baud rate counter, implement the transmission logic, and finally output the serial data.

📋 What You'll Learn

Create an 8-bit data input register called data_in with the value 8'b10101010

Create a baud rate counter variable called baud_counter initialized to 0

Implement the UART transmission logic using a case statement inside an always @(posedge clk) block

Print the serial output bit tx at each clock cycle

💡 Why This Matters

🌍 Real World

UART modules are used in embedded systems and microcontrollers to send data serially between devices like sensors, computers, and communication modules.

💼 Career

Understanding UART design is important for hardware engineers and embedded developers working on communication protocols and device interfacing.

1

DATA SETUP: Create the 8-bit data input

Create a register called data_in and set it to the 8-bit binary value 8'b10101010.

Verilog

# Create a register called data_in and set it to 8'b10101010
// Your code here

Hint

Use reg [7:0] data_in = 8'b10101010; to create the data input register.

2

CONFIGURATION: Add baud rate counter

Add a register called baud_counter and initialize it to 0 inside the uart_tx module.

Verilog

module uart_tx();
  reg [7:0] data_in = 8'b10101010;
  // Add baud_counter register initialized to 0
  // Your code here
endmodule

Hint

Use reg [3:0] baud_counter = 0; to create a 4-bit baud rate counter.

3

CORE LOGIC: Implement UART transmission logic

Inside the uart_tx module, add an always @(posedge clk) block. Use a case statement on a 4-bit bit_index register to send the start bit (0), the 8 data bits from data_in, and the stop bit (1) on the tx output.

Verilog

module uart_tx();
  reg [7:0] data_in = 8'b10101010;
  reg [3:0] baud_counter = 0;
  // Add bit_index register and tx output
  // Add always block with case statement for UART bits
  // Your code here
endmodule

Hint

Use a case statement inside an always @(posedge clk) block to assign tx bits based on bit_index.

4

OUTPUT: Display the serial output bit

Add a initial block to simulate the clock and print the tx output at each clock cycle using $display.

Verilog

module uart_tx();
  reg [7:0] data_in = 8'b10101010;
  reg [3:0] baud_counter = 0;
  reg [3:0] bit_index = 0;
  reg tx = 1'b1;

  always @(posedge clk) begin
    case (bit_index)
      4'd0: tx <= 1'b0; // start bit
      4'd1: tx <= data_in[0];
      4'd2: tx <= data_in[1];
      4'd3: tx <= data_in[2];
      4'd4: tx <= data_in[3];
      4'd5: tx <= data_in[4];
      4'd6: tx <= data_in[5];
      4'd7: tx <= data_in[6];
      4'd8: tx <= data_in[7];
      4'd9: tx <= 1'b1; // stop bit
      default: tx <= 1'b1;
    endcase

    if (baud_counter == 4'd15) begin
      baud_counter <= 0;
      if (bit_index < 4'd9) bit_index <= bit_index + 1;
      else bit_index <= 0;
    end else begin
      baud_counter <= baud_counter + 1;
    end
  end

  // Add initial block to simulate clock and print tx
  // Your code here
endmodule

Hint

Use an initial block with $display and $monitor to print the tx output at each clock cycle.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily