UART transmitter module in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output waveform of the UART TX line?

Given the UART transmitter module sends the byte 8'hA5 with 1 start bit, 8 data bits, no parity, and 1 stop bit, what is the sequence of bits on the tx line?

Verilog

module uart_tx(input clk, input rst, input [7:0] data, input send, output reg tx);
  // Simplified UART TX logic
  // Start bit = 0, data LSB first, stop bit = 1
  // Data to send: 8'hA5 = 10100101b
endmodule

A 0 1 0 1 0 0 1 0 1 1

B 1 0 1 0 0 1 0 1 0 0

C 0 1 0 1 0 0 1 0 1 0

D 1 0 1 0 0 1 0 1 1 1

💡 Hint

Remember UART sends a start bit (0), then data bits LSB first, then stop bit (1).

The start bit is 0, then the data bits of 8'hA5 (binary 10100101) sent LSB first: 1 0 1 0 0 1 0 1, then stop bit 1. So the full sequence is 0 1 0 1 0 0 1 0 1 1.

🧠 Conceptual

intermediate

What is the role of the baud rate generator in a UART transmitter?

In a UART transmitter module, what does the baud rate generator do?

A It stores the data byte to be transmitted.

B It generates the clock enable signal to time the transmission bits correctly.

C It converts parallel data into serial data.

D It detects errors in the received data.

💡 Hint

Think about how UART timing is controlled for sending bits at the right speed.

The baud rate generator creates a timing pulse that controls when each bit is sent, ensuring the transmitter sends bits at the correct speed.

🔧 Debug

advanced

Why does this UART transmitter code fail to send the stop bit?

Examine the following UART transmitter snippet. Why does it never send the stop bit?

Verilog

always @(posedge clk or posedge rst) begin
  if (rst) begin
    state <= IDLE;
    tx <= 1'b1;
  end else if (baud_tick) begin
    case(state)
      IDLE: if (send) begin
        state <= START;
        tx <= 0;
      end
      START: state <= DATA;
      DATA: if (bit_index == 7) state <= IDLE; else bit_index <= bit_index + 1;
    endcase
  end
end

A Because the baud_tick signal is not generated.

B Because the tx line is never set to 0 for the start bit.

C Because the stop bit state is missing from the state machine.

D Because the bit_index counter resets too early.

💡 Hint

Check if the state machine covers all UART transmission phases.

The code does not have a state to send the stop bit, so after sending data bits it returns to IDLE without sending stop bit.

📝 Syntax

advanced

Which option correctly declares a parameter for baud rate in Verilog?

Choose the correct syntax to declare a parameter BAUD_RATE with value 9600 in Verilog.

A param BAUD_RATE = 9600;

B parameter int BAUD_RATE = 9600;

C localparam BAUD_RATE = 9600

D parameter BAUD_RATE = 9600;

💡 Hint

Remember Verilog parameter syntax ends with a semicolon and does not use int keyword.

In Verilog, parameters are declared with parameter NAME = value;. The int keyword is SystemVerilog, and param is invalid.

🚀 Application

expert

How many clock cycles are needed to send one byte at 115200 baud with a 50 MHz clock?

A UART transmitter runs at 50 MHz clock and sends data at 115200 baud. How many clock cycles does it take to send one byte including 1 start bit and 1 stop bit?

A 4340 clock cycles

B 435 clock cycles

C 434 clock cycles

D 4350 clock cycles

💡 Hint

Calculate clock cycles per bit, then multiply by total bits (start + 8 data + stop).

Clock cycles per bit = 50,000,000 / 115,200 ≈ 434. Total bits = 1 + 8 + 1 = 10. Total cycles = 434 * 10 = 4340.

Practice

1. What is the main purpose of a UART transmitter module in Verilog?

easy

A. To send data bit by bit with start and stop bits

B. To receive data from a serial line

C. To generate a clock signal

D. To store data in memory

Solution

1. Step 1: Understand UART transmitter function

   A UART transmitter sends data serially, one bit at a time, adding start and stop bits to frame the data.

2. Step 2: Compare options with UART role

   Only To send data bit by bit with start and stop bits describes sending data bit by bit with start and stop bits, which matches UART transmitter behavior.

3. Final Answer:

   To send data bit by bit with start and stop bits -> Option A

4. Quick Check:

   UART transmitter = sends framed serial data [OK]

Hint: UART transmitter sends framed bits serially [OK]

Common Mistakes:

• Confusing transmitter with receiver
• Thinking UART generates clock
• Assuming it stores data

2. Which of the following is the correct Verilog syntax to declare a 1-bit output named tx in a UART transmitter module?

easy

A. output [7:0] tx;

B. input wire tx;

C. output reg tx;

D. wire tx; output;

Solution

1. Step 1: Identify output declaration for 1-bit signal

   In Verilog, a 1-bit output that can change inside always blocks is declared as output reg tx;.

2. Step 2: Check other options

   input wire tx; declares input, not output. output [7:0] tx; declares 8 bits, not 1. wire tx; output; is invalid syntax.

3. Final Answer:

   output reg tx; -> Option C

4. Quick Check:

   1-bit output reg = output reg tx; [OK]

Hint: Use 'output reg' for 1-bit output driven in always block [OK]

Common Mistakes:

• Using input instead of output
• Declaring wrong bit width
• Incorrect syntax order

3. Given this simplified UART transmitter snippet, what will be the value of tx after sending the start bit?

reg tx = 1;
reg [3:0] bit_count = 0;
always @(posedge clk) begin
  if (bit_count == 0) tx <= 0; // start bit
  else tx <= 1; // stop bit or idle
  bit_count <= bit_count + 1;
end

medium

A. 0

B. 1

C. Undefined

D. Remains unchanged

Solution

1. Step 1: Analyze bit_count and tx assignment

   When bit_count is 0, tx is set to 0 (start bit).

2. Step 2: Determine tx value after start bit

   At the first clock edge, bit_count is 0, so tx becomes 0.

3. Final Answer:

   0 -> Option A

4. Quick Check:

   Start bit = 0 on tx line [OK]

Hint: Start bit always drives tx low (0) [OK]

Common Mistakes:

• Assuming tx stays 1 initially
• Confusing bit_count values
• Ignoring synchronous assignment

4. Identify the error in this UART transmitter code snippet:

always @(posedge clk) begin
  if (start) begin
    tx <= 0; // start bit
    busy <= 1;
  end else if (bit_count == 8) begin
    tx <= 1; // stop bit
    busy <= 0;
  end
  bit_count <= bit_count + 1;
end

medium

A. tx is never set to 0

B. bit_count increments even when not transmitting

C. busy signal is never set

D. Missing reset for bit_count

Solution

1. Step 1: Check bit_count increment logic

   bit_count increments every clock cycle regardless of start or transmission state.

2. Step 2: Understand impact on transmission

   This causes bit_count to increase even when not transmitting, which is incorrect behavior.

3. Final Answer:

   bit_count increments even when not transmitting -> Option B

4. Quick Check:

   bit_count should increment only during transmission [OK]

Hint: Increment counters only when transmitting [OK]

Common Mistakes:

• Incrementing counters unconditionally
• Not resetting bit_count properly
• Ignoring busy signal control

5. You want to modify a UART transmitter module to send 9 data bits instead of 8. Which changes are necessary?

• Adjust bit counter width
• Change stop bit timing
• Modify data register size
• Update start bit logic

Which combination is correct?

hard

A. Adjust bit counter width and modify data register size only

B. Update start bit logic only

C. Change stop bit timing and update start bit logic only

D. Adjust bit counter width, modify data register size, and change stop bit timing

Solution

1. Step 1: Adjust bit counter and data register

   To send 9 bits, the bit counter must count to 9 and the data register must hold 9 bits.

2. Step 2: Change stop bit timing

   Stop bit timing depends on total bits sent; sending 9 bits changes timing, so it must be updated.

3. Step 3: Evaluate start bit logic

   Start bit logic remains the same because it always signals the start of transmission.

4. Final Answer:

   Adjust bit counter width, modify data register size, and change stop bit timing -> Option D

5. Quick Check:

   9-bit data needs counter, register, and timing updates [OK]

Hint: Update counter, register size, and timing for extra bits [OK]

Common Mistakes:

• Forgetting to change counter width
• Ignoring stop bit timing
• Changing start bit logic unnecessarily