Edge detector (rising, falling, both) in Verilog - Step-by-Step Execution

Concept Flow - Edge detector (rising, falling, both)

Input signal changes

↓

Store previous input

↓

Compare current and previous

↓

If current=1 & previous=0

→Rising edge detected

↓

If current=0 & previous=1

→Falling edge detected

↓

Else

→No edge

↓

Output edge signal accordingly

The edge detector compares the current input with the previous input to find rising, falling, or both edges and outputs a signal accordingly.

Execution Sample

Verilog

module edge_detector(
  input clk, input signal_in,
  output reg rising_edge,
  output reg falling_edge
);
  reg prev_signal;
  always @(posedge clk) begin
    rising_edge <= signal_in & ~prev_signal;
    falling_edge <= ~signal_in & prev_signal;
    prev_signal <= signal_in;
  end
endmodule

Detects rising and falling edges of signal_in on clock's rising edge.

Execution Table

Step	clk	signal_in	prev_signal	rising_edge	falling_edge	Action
1	0	0	x	0	0	Initial state, prev_signal unknown
2	1 (posedge)	0	0	0 & ~0=0	~0 & 0=0	No edge, prev_signal updated to 0
3	0	1	0	0	0	No clock edge, no update
4	1 (posedge)	1	0	1 & ~0=1	~1 & 0=0	Rising edge detected, prev_signal=1
5	0	1	1	1	0	No clock edge, no update
6	1 (posedge)	0	1	0 & ~1=0	~0 & 1=1	Falling edge detected, prev_signal=0
7	0	0	0	0	0	No clock edge, no update
8	1 (posedge)	0	0	0 & ~0=0	~0 & 0=0	No edge, prev_signal=0
9	1 (posedge)	1	0	1 & ~0=1	~1 & 0=0	Rising edge detected again
10	1 (posedge)	0	1	0 & ~1=0	~0 & 1=1	Falling edge detected again

💡 Simulation ends after 10 steps showing rising and falling edges detection on clock edges.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	After 8	After 9	Final
prev_signal	x	0	0	0	1	1	0	0	0	0	0
rising_edge	0	0	0	1	1	0	0	0	1	1	1
falling_edge	0	0	0	0	0	1	1	0	0	0	1

Key Moments - 3 Insights

Why does the rising_edge signal only become 1 when clk has a rising edge?

Because the always block triggers only on the positive edge of clk, so the signals update only then, as shown in execution_table rows with clk=1 (posedge).

Why do we need to store prev_signal?

We compare current signal_in with prev_signal to detect edges. Without prev_signal, we can't know if signal_in changed from 0 to 1 or 1 to 0, as seen in execution_table comparing signal_in and prev_signal.

What happens if signal_in stays the same for multiple clock cycles?

No edge is detected; rising_edge and falling_edge stay 0, because the condition for edges requires a change between current and previous signal_in, as shown in steps where signal_in equals prev_signal.

Visual Quiz - 3 Questions

Look at the execution_table at step 4. What is the value of rising_edge and why?

A rising_edge=1 because signal_in changed from 0 to 1

B rising_edge=0 because signal_in did not change

C rising_edge=1 because signal_in changed from 1 to 0

D rising_edge=0 because prev_signal is unknown

💡 Hint

Check step 4 in execution_table where signal_in=1 and prev_signal=0, rising_edge = signal_in & ~prev_signal

At which step does falling_edge first become 1?

A Step 4

B Step 2

C Step 6

D Step 9

💡 Hint

Look for the first row where falling_edge=1 in execution_table

If prev_signal was not updated inside the always block, what would happen to edge detection?

A Only rising edges would be detected

B No edges would be detected after the first clock

C Edges would still be detected correctly

D Only falling edges would be detected

💡 Hint

Refer to variable_tracker for prev_signal updates and their importance

Concept Snapshot

Edge detector in Verilog:
- Store previous input signal
- On clock rising edge, compare current and previous
- rising_edge = current & ~previous
- falling_edge = ~current & previous
- Outputs 1 for one clock cycle on detected edge

Full Transcript

This visual execution shows how an edge detector in Verilog works by storing the previous input signal and comparing it with the current input on each rising clock edge. When the input changes from 0 to 1, the rising_edge output becomes 1 for one clock cycle. When the input changes from 1 to 0, the falling_edge output becomes 1 for one clock cycle. The execution table traces signal_in, prev_signal, rising_edge, and falling_edge step-by-step, showing exactly when edges are detected. The variable tracker highlights how prev_signal updates each clock cycle, which is essential for detecting edges. Key moments clarify why updates happen only on clock edges and why storing previous input is necessary. The quiz tests understanding of these steps and the importance of prev_signal updates. This helps beginners see exactly how edge detection logic works in hardware description language Verilog.

Practice

1. What does a rising edge detector in Verilog detect?
always @(posedge clk) is often used in such detectors.

easy

A. Both 0 to 1 and 1 to 0 changes

B. A change of signal from 1 to 0

C. A change of signal from 0 to 1

D. No change in signal

Solution

1. Step 1: Understand rising edge meaning

   A rising edge means the signal changes from low (0) to high (1).

2. Step 2: Relate to Verilog edge detection

   The posedge keyword triggers on this rising edge.

3. Final Answer:

   A change of signal from 0 to 1 -> Option C

4. Quick Check:

   Rising edge = 0 to 1 transition [OK]

Hint: Rising edge means signal goes from 0 to 1 [OK]

Common Mistakes:

• Confusing rising edge with falling edge
• Thinking it detects no change
• Mixing up posedge and negedge keywords

2. Which of the following Verilog code snippets correctly detects a falling edge of signal sig?

easy

A. always @(negedge sig) begin // detect falling edge end

B. always @(posedge sig) begin // detect falling edge end

C. always @(sig) begin // detect falling edge end

D. always @(posedge clk) if (sig == 1) // detect falling edge

Solution

1. Step 1: Identify falling edge keyword

   Falling edge detection uses negedge in Verilog.

2. Step 2: Match code to falling edge

   always @(negedge sig) begin // detect falling edge end uses always @(negedge sig), which triggers on signal going from 1 to 0.

3. Final Answer:

   always @(negedge sig) begin // detect falling edge end -> Option A

4. Quick Check:

   Falling edge = negedge keyword [OK]

Hint: Use negedge to detect falling edges in Verilog [OK]

Common Mistakes:

• Using posedge for falling edge detection
• Using level-sensitive sensitivity list
• Confusing signal and clock edges

3. Given this Verilog code snippet for detecting both edges of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire edge_detect = sig ^ sig_d;

What is the value of edge_detect when sig changes from 0 to 1?

medium

A. 1

B. 0

C. Undefined (X)

D. Remains previous value

Solution

1. Step 1: Understand delayed signal sig_d

   sig_d holds previous clock cycle's sig value.

2. Step 2: Calculate XOR for edge detection

   When sig changes from 0 to 1, XOR with previous 0 gives 1, indicating an edge.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   sig ^ sig_d = 1 on edge [OK]

Hint: XOR current and delayed signal to detect edges [OK]

Common Mistakes:

• Forgetting to delay signal before XOR
• Assuming edge_detect stays 0 on change
• Confusing XOR with AND or OR

4. Identify the error in this Verilog code intended to detect a rising edge of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire rising_edge = sig & ~sig_d;

medium

A. Using blocking assignment instead of non-blocking

B. Incorrect logic for rising edge detection

C. No sensitivity list for wire rising_edge

D. Missing initial value for sig_d

Solution

1. Step 1: Analyze rising edge logic

   Rising edge is when signal changes from 0 to 1, so previous was 0 and current is 1.

2. Step 2: Check given logic expression

   The expression sig & ~sig_d correctly detects rising edge by current high and previous low.

3. Step 3: Re-examine for errors

   Actually, the logic is correct; the error is elsewhere.

4. Step 4: Identify actual error

   Missing initial value for sig_d can cause unknown behavior at start.

5. Final Answer:

   Missing initial value for sig_d -> Option D

6. Quick Check:

   Initialize delayed signal to avoid unknowns [OK]

Hint: Initialize delayed signals to avoid unknown start values [OK]

Common Mistakes:

• Assuming logic expression is wrong
• Ignoring initial values for registers
• Confusing blocking and non-blocking assignments

5. You want to design a Verilog module that outputs a pulse of 1 clock cycle width whenever sig changes either from 0 to 1 or 1 to 0. Which code snippet correctly implements this?

hard

A. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig & ~sig_d;

B. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig ^ sig_d;

C. wire edge_pulse = (sig == 1) ? 1 : 0;

D. always @(posedge sig) edge_pulse = 1;

Solution

1. Step 1: Understand requirement for both edges

   The pulse should be high for one clock cycle on any signal change (rising or falling).

2. Step 2: Analyze each option

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; uses XOR between current and delayed signal, which is 1 only on change, producing a 1-cycle pulse.

3. Step 3: Confirm other options

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig & ~sig_d; detects only rising edge; C is level detection; D triggers on posedge of sig, not clock, and lacks pulse width control.

4. Final Answer:

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; -> Option B

5. Quick Check:

   XOR current and delayed signal for both edges pulse [OK]

Hint: XOR current and delayed signals for both edges pulse [OK]

Common Mistakes:

• Using only rising edge logic for both edges
• Triggering on signal edge instead of clock
• Not producing single clock cycle pulse