Edge detector (rising, falling, both) in Verilog - Mini Project: Build & Apply

Edge detector (rising, falling, both)

📖 Scenario: You are designing a simple digital circuit that detects changes in a signal. This is useful in many electronics projects where you want to know when a signal goes from low to high (rising edge), high to low (falling edge), or both.

🎯 Goal: You will build a Verilog module that detects rising edges, falling edges, or both edges of an input signal. You will write code step-by-step to create the signal input, add configuration for edge detection mode, implement the detection logic, and finally output the detected edges.

📋 What You'll Learn

Create a signal input register called signal.

Create a configuration register called mode to select edge detection type.

Implement edge detection logic using previous signal state.

Output the detected edge as a 1-bit signal called edge_detected.

Support three modes: rising edge only, falling edge only, and both edges.

💡 Why This Matters

🌍 Real World

Edge detection is used in digital circuits to trigger actions when signals change, such as button presses or sensor outputs.

💼 Career

Understanding edge detection is important for hardware engineers and FPGA developers working on digital design and embedded systems.

1

DATA SETUP: Create the input signal register

Create a 1-bit register called signal and initialize it to 0.

Verilog

reg signal = 0;  // Your code here

Hint

Use reg to declare a register and set it to 0.

2

CONFIGURATION: Add mode register for edge detection type

Create a 2-bit register called mode to select edge detection type. Use 2'b00 for rising edge, 2'b01 for falling edge, and 2'b10 for both edges.

Verilog

reg signal = 0;
reg [1:0] mode = 2'b00;  // Your code here

Hint

Use reg [1:0] to declare a 2-bit register and initialize it to 2'b00.

3

CORE LOGIC: Implement edge detection using previous signal state

Create a 1-bit register called prev_signal to store the previous value of signal. Then write an always block triggered on the positive edge of a clock called clk. Inside, update prev_signal with the current signal. Then create a wire called edge_detected that is 1 when the selected edge(s) occur based on mode.

Verilog

reg signal = 0;
reg [1:0] mode = 2'b00;
reg prev_signal = 0;

// Your code here

Hint

Use always @(posedge clk) to update prev_signal. Use a wire with conditions to detect edges based on mode.

4

OUTPUT: Display the detected edge signal

Write a statement to display the value of edge_detected whenever it changes.

Verilog

reg signal = 0;
reg [1:0] mode = 2'b00;
reg prev_signal = 0;

always @(posedge clk) begin
    prev_signal <= signal;
end

wire edge_detected = ((mode == 2'b00) && (signal == 1 && prev_signal == 0)) ||
                     ((mode == 2'b01) && (signal == 0 && prev_signal == 1)) ||
                     ((mode == 2'b10) && (signal != prev_signal));

// Your code here

Hint

Use $display inside an always block triggered by edge_detected changes.

Practice

1. What does a rising edge detector in Verilog detect?
always @(posedge clk) is often used in such detectors.

easy

A. Both 0 to 1 and 1 to 0 changes

B. A change of signal from 1 to 0

C. A change of signal from 0 to 1

D. No change in signal

Solution

1. Step 1: Understand rising edge meaning

   A rising edge means the signal changes from low (0) to high (1).

2. Step 2: Relate to Verilog edge detection

   The posedge keyword triggers on this rising edge.

3. Final Answer:

   A change of signal from 0 to 1 -> Option C

4. Quick Check:

   Rising edge = 0 to 1 transition [OK]

Hint: Rising edge means signal goes from 0 to 1 [OK]

Common Mistakes:

• Confusing rising edge with falling edge
• Thinking it detects no change
• Mixing up posedge and negedge keywords

2. Which of the following Verilog code snippets correctly detects a falling edge of signal sig?

easy

A. always @(negedge sig) begin // detect falling edge end

B. always @(posedge sig) begin // detect falling edge end

C. always @(sig) begin // detect falling edge end

D. always @(posedge clk) if (sig == 1) // detect falling edge

Solution

1. Step 1: Identify falling edge keyword

   Falling edge detection uses negedge in Verilog.

2. Step 2: Match code to falling edge

   always @(negedge sig) begin // detect falling edge end uses always @(negedge sig), which triggers on signal going from 1 to 0.

3. Final Answer:

   always @(negedge sig) begin // detect falling edge end -> Option A

4. Quick Check:

   Falling edge = negedge keyword [OK]

Hint: Use negedge to detect falling edges in Verilog [OK]

Common Mistakes:

• Using posedge for falling edge detection
• Using level-sensitive sensitivity list
• Confusing signal and clock edges

3. Given this Verilog code snippet for detecting both edges of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire edge_detect = sig ^ sig_d;

What is the value of edge_detect when sig changes from 0 to 1?

medium

A. 1

B. 0

C. Undefined (X)

D. Remains previous value

Solution

1. Step 1: Understand delayed signal sig_d

   sig_d holds previous clock cycle's sig value.

2. Step 2: Calculate XOR for edge detection

   When sig changes from 0 to 1, XOR with previous 0 gives 1, indicating an edge.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   sig ^ sig_d = 1 on edge [OK]

Hint: XOR current and delayed signal to detect edges [OK]

Common Mistakes:

• Forgetting to delay signal before XOR
• Assuming edge_detect stays 0 on change
• Confusing XOR with AND or OR

4. Identify the error in this Verilog code intended to detect a rising edge of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire rising_edge = sig & ~sig_d;

medium

A. Using blocking assignment instead of non-blocking

B. Incorrect logic for rising edge detection

C. No sensitivity list for wire rising_edge

D. Missing initial value for sig_d

Solution

1. Step 1: Analyze rising edge logic

   Rising edge is when signal changes from 0 to 1, so previous was 0 and current is 1.

2. Step 2: Check given logic expression

   The expression sig & ~sig_d correctly detects rising edge by current high and previous low.

3. Step 3: Re-examine for errors

   Actually, the logic is correct; the error is elsewhere.

4. Step 4: Identify actual error

   Missing initial value for sig_d can cause unknown behavior at start.

5. Final Answer:

   Missing initial value for sig_d -> Option D

6. Quick Check:

   Initialize delayed signal to avoid unknowns [OK]

Hint: Initialize delayed signals to avoid unknown start values [OK]

Common Mistakes:

• Assuming logic expression is wrong
• Ignoring initial values for registers
• Confusing blocking and non-blocking assignments

5. You want to design a Verilog module that outputs a pulse of 1 clock cycle width whenever sig changes either from 0 to 1 or 1 to 0. Which code snippet correctly implements this?

hard

A. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig & ~sig_d;

B. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig ^ sig_d;

C. wire edge_pulse = (sig == 1) ? 1 : 0;

D. always @(posedge sig) edge_pulse = 1;

Solution

1. Step 1: Understand requirement for both edges

   The pulse should be high for one clock cycle on any signal change (rising or falling).

2. Step 2: Analyze each option

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; uses XOR between current and delayed signal, which is 1 only on change, producing a 1-cycle pulse.

3. Step 3: Confirm other options

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig & ~sig_d; detects only rising edge; C is level detection; D triggers on posedge of sig, not clock, and lacks pulse width control.

4. Final Answer:

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; -> Option B

5. Quick Check:

   XOR current and delayed signal for both edges pulse [OK]

Hint: XOR current and delayed signals for both edges pulse [OK]

Common Mistakes:

• Using only rising edge logic for both edges
• Triggering on signal edge instead of clock
• Not producing single clock cycle pulse