Edge detector (rising, falling, both) in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to detect a rising edge on signal sig.

Verilog

wire rising_edge = sig & ~[1];

Drag options to blanks, or click blank then click option'

Aclk

Bsig

Csig_d

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using the current signal instead of the delayed signal for comparison.

Confusing rising edge with falling edge logic.

To detect a rising edge, we compare the current signal sig with its delayed version sig_d. The rising edge occurs when sig is high and sig_d is low.

2fill in blank

medium

Complete the code to detect a falling edge on signal sig.

Verilog

wire falling_edge = ~sig & [1];

Drag options to blanks, or click blank then click option'

Asig

Bsig_d

Cclk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using the current signal twice instead of using the delayed signal.

Mixing up the logic for rising and falling edges.

A falling edge is detected when the current signal sig is low and the delayed signal sig_d is high.

3fill in blank

hard

Fix the error in the always block that updates the delayed signal sig_d.

Verilog

always @(posedge clk or posedge rst) begin
  if (rst)
    sig_d <= 1'b0;
  else
    sig_d <= [1];
end

Drag options to blanks, or click blank then click option'

Arst

Bsig_d

Cclk

Dsig

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning sig_d to itself causing no update.

Assigning sig_d to clock or reset signals.

The delayed signal sig_d should be updated with the current value of sig on each clock cycle.

4fill in blank

hard

Fill both blanks to create a module that detects both rising and falling edges of sig.

Verilog

module edge_detector(
  input wire clk,
  input wire rst,
  input wire sig,
  output wire rising,
  output wire falling
);

reg [1];

always @(posedge clk or posedge rst) begin
  if (rst)
    [2] <= 1'b0;
  else
    [2] <= sig;
end

assign rising = sig & ~sig_d;
assign falling = ~sig & sig_d;

endmodule

Drag options to blanks, or click blank then click option'

Asig_d

Bsig

Cclk

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using different names for declaration and assignment.

Not declaring the delayed signal as a register.

The delayed signal sig_d is declared as a register and updated inside the always block to hold the previous value of sig.

5fill in blank

hard

Fill all three blanks to complete the module that outputs a signal edge_detected which is high on any edge (rising or falling) of sig.

Verilog

module edge_detector(
  input wire clk,
  input wire rst,
  input wire sig,
  output wire edge_detected
);

reg [1];

always @(posedge clk or posedge rst) begin
  if (rst)
    [2] <= 1'b0;
  else
    [2] <= sig;
end

assign edge_detected = sig ^ [3];

endmodule

Drag options to blanks, or click blank then click option'

Asig_d

Bsig

Drst

Attempts:

3 left

💡 Hint

Common Mistakes

Using different names for delayed signal in declaration and assignment.

Using wrong signals in the XOR operation.

The delayed signal sig_d is declared and updated to hold the previous value of sig. The XOR operation between sig and sig_d detects any edge.

Practice

1. What does a rising edge detector in Verilog detect?
always @(posedge clk) is often used in such detectors.

easy

A. Both 0 to 1 and 1 to 0 changes

B. A change of signal from 1 to 0

C. A change of signal from 0 to 1

D. No change in signal

Solution

1. Step 1: Understand rising edge meaning

   A rising edge means the signal changes from low (0) to high (1).

2. Step 2: Relate to Verilog edge detection

   The posedge keyword triggers on this rising edge.

3. Final Answer:

   A change of signal from 0 to 1 -> Option C

4. Quick Check:

   Rising edge = 0 to 1 transition [OK]

Hint: Rising edge means signal goes from 0 to 1 [OK]

Common Mistakes:

• Confusing rising edge with falling edge
• Thinking it detects no change
• Mixing up posedge and negedge keywords

2. Which of the following Verilog code snippets correctly detects a falling edge of signal sig?

easy

A. always @(negedge sig) begin // detect falling edge end

B. always @(posedge sig) begin // detect falling edge end

C. always @(sig) begin // detect falling edge end

D. always @(posedge clk) if (sig == 1) // detect falling edge

Solution

1. Step 1: Identify falling edge keyword

   Falling edge detection uses negedge in Verilog.

2. Step 2: Match code to falling edge

   always @(negedge sig) begin // detect falling edge end uses always @(negedge sig), which triggers on signal going from 1 to 0.

3. Final Answer:

   always @(negedge sig) begin // detect falling edge end -> Option A

4. Quick Check:

   Falling edge = negedge keyword [OK]

Hint: Use negedge to detect falling edges in Verilog [OK]

Common Mistakes:

• Using posedge for falling edge detection
• Using level-sensitive sensitivity list
• Confusing signal and clock edges

3. Given this Verilog code snippet for detecting both edges of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire edge_detect = sig ^ sig_d;

What is the value of edge_detect when sig changes from 0 to 1?

medium

A. 1

B. 0

C. Undefined (X)

D. Remains previous value

Solution

1. Step 1: Understand delayed signal sig_d

   sig_d holds previous clock cycle's sig value.

2. Step 2: Calculate XOR for edge detection

   When sig changes from 0 to 1, XOR with previous 0 gives 1, indicating an edge.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   sig ^ sig_d = 1 on edge [OK]

Hint: XOR current and delayed signal to detect edges [OK]

Common Mistakes:

• Forgetting to delay signal before XOR
• Assuming edge_detect stays 0 on change
• Confusing XOR with AND or OR

4. Identify the error in this Verilog code intended to detect a rising edge of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire rising_edge = sig & ~sig_d;

medium

A. Using blocking assignment instead of non-blocking

B. Incorrect logic for rising edge detection

C. No sensitivity list for wire rising_edge

D. Missing initial value for sig_d

Solution

1. Step 1: Analyze rising edge logic

   Rising edge is when signal changes from 0 to 1, so previous was 0 and current is 1.

2. Step 2: Check given logic expression

   The expression sig & ~sig_d correctly detects rising edge by current high and previous low.

3. Step 3: Re-examine for errors

   Actually, the logic is correct; the error is elsewhere.

4. Step 4: Identify actual error

   Missing initial value for sig_d can cause unknown behavior at start.

5. Final Answer:

   Missing initial value for sig_d -> Option D

6. Quick Check:

   Initialize delayed signal to avoid unknowns [OK]

Hint: Initialize delayed signals to avoid unknown start values [OK]

Common Mistakes:

• Assuming logic expression is wrong
• Ignoring initial values for registers
• Confusing blocking and non-blocking assignments

5. You want to design a Verilog module that outputs a pulse of 1 clock cycle width whenever sig changes either from 0 to 1 or 1 to 0. Which code snippet correctly implements this?

hard

A. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig & ~sig_d;

B. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig ^ sig_d;

C. wire edge_pulse = (sig == 1) ? 1 : 0;

D. always @(posedge sig) edge_pulse = 1;

Solution

1. Step 1: Understand requirement for both edges

   The pulse should be high for one clock cycle on any signal change (rising or falling).

2. Step 2: Analyze each option

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; uses XOR between current and delayed signal, which is 1 only on change, producing a 1-cycle pulse.

3. Step 3: Confirm other options

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig & ~sig_d; detects only rising edge; C is level detection; D triggers on posedge of sig, not clock, and lacks pulse width control.

4. Final Answer:

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; -> Option B

5. Quick Check:

   XOR current and delayed signal for both edges pulse [OK]

Hint: XOR current and delayed signals for both edges pulse [OK]

Common Mistakes:

• Using only rising edge logic for both edges
• Triggering on signal edge instead of clock
• Not producing single clock cycle pulse