Edge detector (rising, falling, both) in Verilog - Deep Dive

Overview - Edge detector (rising, falling, both)

What is it?

An edge detector in Verilog is a circuit that identifies when a signal changes from low to high (rising edge), high to low (falling edge), or both. It outputs a short pulse exactly when this change happens. This helps digital systems react only at the moment of change, not while the signal stays steady.

Why it matters

Without edge detectors, digital circuits might miss important changes or react multiple times to the same signal level. For example, a button press might be counted many times instead of once. Edge detectors ensure precise timing and control, which is critical in hardware design for reliable and efficient operation.

Where it fits

Before learning edge detectors, you should understand basic Verilog syntax, signals, and clocked processes. After mastering edge detectors, you can explore more complex timing controls, state machines, and synchronization techniques in digital design.

Mental Model

Core Idea

An edge detector watches a signal and tells you exactly when it flips from 0 to 1, 1 to 0, or both, by comparing the current and previous values.

Think of it like...

It's like noticing when a traffic light changes color: you only react at the moment it switches from red to green or green to red, not while it stays the same color.

Signal:   ──────▁▁▁▁▁▁───────▔▔▔▔▔▔─────
Prev:     ──────▁▁▁▁▁▁───────▁▁▁▁▁▁─────
Edge Det:       ↑           ↓          
(↑ = rising edge, ↓ = falling edge)

Build-Up - 7 Steps

1

Foundation

Understanding signal changes over time

Concept: Signals in digital circuits change values over time, and detecting these changes is key to controlling hardware.

In Verilog, signals can be 0 or 1. When a signal changes from 0 to 1, it's called a rising edge. When it changes from 1 to 0, it's a falling edge. We need to detect these changes to trigger actions exactly at those moments.

Result

You can now identify when a signal changes state by comparing its current and previous values.

Understanding that signals have history and current state is the foundation for detecting edges.

2

Foundation

Storing previous signal value in Verilog

Concept: To detect edges, you must remember the signal's previous value using a register updated every clock cycle.

Use a register to save the signal's value at each clock tick. For example: reg prev_signal; always @(posedge clk) begin prev_signal <= signal; end This lets you compare current 'signal' with 'prev_signal' to find changes.

Result

You have a way to track signal changes by comparing current and stored previous values.

Knowing how to store past signal values enables edge detection by comparison.

3

Intermediate

Detecting rising edges in Verilog

🤔Before reading on: do you think checking if current signal is 1 and previous is 0 detects a rising edge? Commit to your answer.

Concept: A rising edge happens when the signal changes from 0 to 1, so detect it by comparing current and previous values.

Example code to detect rising edge: wire rising_edge = signal & ~prev_signal; This expression is true only when 'signal' is 1 and 'prev_signal' is 0, indicating a rising edge.

Result

The 'rising_edge' wire pulses high for one clock cycle exactly when the signal rises.

Understanding the boolean logic for rising edges helps create precise one-cycle pulses.

4

Intermediate

Detecting falling edges in Verilog

🤔Before reading on: do you think checking if current signal is 0 and previous is 1 detects a falling edge? Commit to your answer.

Concept: A falling edge happens when the signal changes from 1 to 0, so detect it by comparing current and previous values.

Example code to detect falling edge: wire falling_edge = ~signal & prev_signal; This expression is true only when 'signal' is 0 and 'prev_signal' is 1, indicating a falling edge.

Result

The 'falling_edge' wire pulses high for one clock cycle exactly when the signal falls.

Knowing how to invert signals and compare them reveals falling edges cleanly.

5

Intermediate

Detecting both edges in Verilog

🤔Before reading on: do you think combining rising and falling edge logic with OR detects both edges? Commit to your answer.

Concept: Detecting both edges means detecting either rising or falling edges by combining their conditions.

Example code: wire both_edges = (signal & ~prev_signal) | (~signal & prev_signal); This wire pulses high whenever the signal changes, regardless of direction.

Result

The 'both_edges' wire pulses for one clock cycle on any signal change.

Combining edge conditions with OR captures all transitions efficiently.

6

Advanced

Implementing edge detector in synchronous always block

🤔Before reading on: do you think edge detection logic must be inside a clocked always block to work reliably? Commit to your answer.

Concept: Edge detection should be done synchronously to avoid glitches and ensure stable output in hardware.

Example Verilog module: module edge_detector( input clk, input signal, output reg rising_edge, output reg falling_edge, output reg both_edges ); reg prev_signal; always @(posedge clk) begin rising_edge <= signal & ~prev_signal; falling_edge <= ~signal & prev_signal; both_edges <= rising_edge | falling_edge; prev_signal <= signal; end endmodule This code updates previous signal and outputs edge pulses synchronized to clock.

Result

Edge signals are clean, glitch-free pulses exactly one clock cycle long.

Synchronizing edge detection to clock prevents timing hazards and ensures reliable hardware behavior.

7

Expert

Handling asynchronous signals and metastability

🤔Before reading on: do you think directly detecting edges on asynchronous inputs is safe in synchronous designs? Commit to your answer.

Concept: Asynchronous signals can cause unpredictable behavior; proper synchronization is needed before edge detection.

Asynchronous inputs must be passed through synchronizer flip-flops to avoid metastability: reg sync_0, sync_1; always @(posedge clk) begin sync_0 <= async_signal; sync_1 <= sync_0; end Then detect edges on 'sync_1' instead of 'async_signal'. This reduces timing errors and ensures stable edge detection.

Result

Edge detection works reliably even with signals coming from outside the clock domain.

Understanding metastability and synchronization is critical for robust edge detection in real hardware.

Under the Hood

Edge detection works by storing the previous value of a signal and comparing it to the current value each clock cycle. When the values differ in a specific way (0 to 1 or 1 to 0), the detector outputs a pulse. Internally, this uses flip-flops to hold the previous state and combinational logic to compare states and generate pulses.

Why designed this way?

This design ensures that edge detection is synchronized to the system clock, avoiding glitches and timing hazards common in asynchronous logic. Early hardware designs without synchronization suffered from unreliable signals. Using registers and clocked logic provides stable, predictable outputs essential for complex digital systems.

┌─────────────┐      ┌─────────────┐      ┌─────────────┐
│ Current Sig │─────▶│   Compare   │─────▶│ Edge Output │
└─────────────┘      │  Logic (XOR)│      └─────────────┘
                     └─────┬───────┘
                           │
┌─────────────┐            │
│ Prev Signal │────────────┘
└─────────────┘

Myth Busters - 4 Common Misconceptions

Quick: Does detecting an edge mean the output stays high as long as the signal is high? Commit yes or no.

Common Belief: Edge detectors output a high signal for the entire time the input is high.

Reality: Edge detectors output a high pulse only for one clock cycle exactly when the signal changes state.

Why it matters: Believing this causes designs to misinterpret edges as level signals, leading to repeated triggers and incorrect behavior.

Quick: Can you detect edges without storing the previous signal value? Commit yes or no.

Common Belief: You can detect edges by looking only at the current signal value.

Reality: Detecting edges requires comparing the current signal to its previous value stored in a register.

Why it matters: Ignoring this leads to designs that cannot detect transitions, missing critical events.

Quick: Is it safe to detect edges directly on asynchronous inputs without synchronization? Commit yes or no.

Common Belief: Edge detection works fine on any input signal without extra handling.

Reality: Asynchronous signals must be synchronized to the clock domain before edge detection to avoid metastability and unreliable outputs.

Why it matters: Failing to synchronize causes unpredictable hardware behavior and hard-to-debug errors.

Quick: Does combining rising and falling edge detection with OR always produce glitch-free output? Commit yes or no.

Common Belief: Simply OR-ing rising and falling edge signals always gives a clean both-edge detector.

Reality: Without proper clock synchronization and careful coding, glitches can occur on the combined output.

Why it matters: Ignoring this can cause false triggers and unstable system behavior.

Expert Zone

1

Edge detectors must be carefully synchronized when used across clock domains to avoid metastability and timing errors.

2

In FPGA designs, using built-in primitives or dedicated hardware for edge detection can improve timing and resource usage.

3

When stacking multiple edge detectors, the order of updating previous signals affects the correctness and timing of outputs.

When NOT to use

Edge detectors are not suitable for signals that change faster than the clock frequency or for analog signals. Instead, use dedicated hardware like pulse shapers, debouncers, or asynchronous event detectors.

Production Patterns

In real systems, edge detectors are combined with debouncing circuits for mechanical inputs, used in interrupt generation, and integrated into state machines to trigger transitions precisely on signal changes.

Connections

Finite State Machines (FSM)

Edge detectors provide precise triggers that FSMs use to change states exactly when inputs change.

Understanding edge detection clarifies how FSMs respond to events only once per input change, preventing repeated transitions.

Signal Synchronization in Digital Systems

Edge detection relies on synchronized signals to avoid metastability and timing errors.

Knowing synchronization principles helps design reliable edge detectors for asynchronous inputs.

Human Reaction to Traffic Lights

Both involve reacting exactly at the moment of change, not during stable states.

This cross-domain connection shows how timing precision is critical in both human and digital systems.

Common Pitfalls

#1 Detecting edges without storing previous signal value

Wrong approach:

wire rising_edge = signal & ~signal; // always zero, no previous value stored

Correct approach:

reg prev_signal;
always @(posedge clk) prev_signal <= signal;
wire rising_edge = signal & ~prev_signal;

Root cause:

Misunderstanding that edge detection requires knowledge of past signal state.

#2 Detecting edges directly on asynchronous inputs without synchronization

Wrong approach:

wire rising_edge = async_signal & ~prev_async_signal; // no synchronizer used

Correct approach:

reg sync_0, sync_1;
always @(posedge clk) begin
sync_0 <= async_signal;
sync_1 <= sync_0;
end
wire rising_edge = sync_1 & ~prev_sync_1;

Root cause:

Ignoring metastability and timing domain crossing issues.

#3 Combining rising and falling edges without clocked registers

Wrong approach:

wire both_edges = (signal & ~prev_signal) | (~signal & prev_signal); // combinational only

Correct approach:

reg rising_edge, falling_edge, both_edges;
always @(posedge clk) begin
rising_edge <= signal & ~prev_signal;
falling_edge <= ~signal & prev_signal;
both_edges <= rising_edge | falling_edge;
prev_signal <= signal;
end

Root cause:

Not synchronizing outputs causes glitches and unstable signals.

Key Takeaways

Edge detectors identify exact moments when signals change by comparing current and previous values.

Storing the previous signal value in a register is essential for reliable edge detection.

Synchronous edge detection prevents glitches and ensures stable hardware behavior.

Asynchronous signals must be synchronized before edge detection to avoid unpredictable results.

Combining rising and falling edge detection requires careful clocked logic to produce clean pulses.

Practice

1. What does a rising edge detector in Verilog detect?
always @(posedge clk) is often used in such detectors.

easy

A. Both 0 to 1 and 1 to 0 changes

B. A change of signal from 1 to 0

C. A change of signal from 0 to 1

D. No change in signal

Solution

1. Step 1: Understand rising edge meaning

   A rising edge means the signal changes from low (0) to high (1).

2. Step 2: Relate to Verilog edge detection

   The posedge keyword triggers on this rising edge.

3. Final Answer:

   A change of signal from 0 to 1 -> Option C

4. Quick Check:

   Rising edge = 0 to 1 transition [OK]

Hint: Rising edge means signal goes from 0 to 1 [OK]

Common Mistakes:

• Confusing rising edge with falling edge
• Thinking it detects no change
• Mixing up posedge and negedge keywords

2. Which of the following Verilog code snippets correctly detects a falling edge of signal sig?

easy

A. always @(negedge sig) begin // detect falling edge end

B. always @(posedge sig) begin // detect falling edge end

C. always @(sig) begin // detect falling edge end

D. always @(posedge clk) if (sig == 1) // detect falling edge

Solution

1. Step 1: Identify falling edge keyword

   Falling edge detection uses negedge in Verilog.

2. Step 2: Match code to falling edge

   always @(negedge sig) begin // detect falling edge end uses always @(negedge sig), which triggers on signal going from 1 to 0.

3. Final Answer:

   always @(negedge sig) begin // detect falling edge end -> Option A

4. Quick Check:

   Falling edge = negedge keyword [OK]

Hint: Use negedge to detect falling edges in Verilog [OK]

Common Mistakes:

• Using posedge for falling edge detection
• Using level-sensitive sensitivity list
• Confusing signal and clock edges

3. Given this Verilog code snippet for detecting both edges of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire edge_detect = sig ^ sig_d;

What is the value of edge_detect when sig changes from 0 to 1?

medium

A. 1

B. 0

C. Undefined (X)

D. Remains previous value

Solution

1. Step 1: Understand delayed signal sig_d

   sig_d holds previous clock cycle's sig value.

2. Step 2: Calculate XOR for edge detection

   When sig changes from 0 to 1, XOR with previous 0 gives 1, indicating an edge.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   sig ^ sig_d = 1 on edge [OK]

Hint: XOR current and delayed signal to detect edges [OK]

Common Mistakes:

• Forgetting to delay signal before XOR
• Assuming edge_detect stays 0 on change
• Confusing XOR with AND or OR

4. Identify the error in this Verilog code intended to detect a rising edge of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire rising_edge = sig & ~sig_d;

medium

A. Using blocking assignment instead of non-blocking

B. Incorrect logic for rising edge detection

C. No sensitivity list for wire rising_edge

D. Missing initial value for sig_d

Solution

1. Step 1: Analyze rising edge logic

   Rising edge is when signal changes from 0 to 1, so previous was 0 and current is 1.

2. Step 2: Check given logic expression

   The expression sig & ~sig_d correctly detects rising edge by current high and previous low.

3. Step 3: Re-examine for errors

   Actually, the logic is correct; the error is elsewhere.

4. Step 4: Identify actual error

   Missing initial value for sig_d can cause unknown behavior at start.

5. Final Answer:

   Missing initial value for sig_d -> Option D

6. Quick Check:

   Initialize delayed signal to avoid unknowns [OK]

Hint: Initialize delayed signals to avoid unknown start values [OK]

Common Mistakes:

• Assuming logic expression is wrong
• Ignoring initial values for registers
• Confusing blocking and non-blocking assignments

5. You want to design a Verilog module that outputs a pulse of 1 clock cycle width whenever sig changes either from 0 to 1 or 1 to 0. Which code snippet correctly implements this?

hard

A. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig & ~sig_d;

B. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig ^ sig_d;

C. wire edge_pulse = (sig == 1) ? 1 : 0;

D. always @(posedge sig) edge_pulse = 1;

Solution

1. Step 1: Understand requirement for both edges

   The pulse should be high for one clock cycle on any signal change (rising or falling).

2. Step 2: Analyze each option

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; uses XOR between current and delayed signal, which is 1 only on change, producing a 1-cycle pulse.

3. Step 3: Confirm other options

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig & ~sig_d; detects only rising edge; C is level detection; D triggers on posedge of sig, not clock, and lacks pulse width control.

4. Final Answer:

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; -> Option B

5. Quick Check:

   XOR current and delayed signal for both edges pulse [OK]

Hint: XOR current and delayed signals for both edges pulse [OK]

Common Mistakes:

• Using only rising edge logic for both edges
• Triggering on signal edge instead of clock
• Not producing single clock cycle pulse