Edge detector (rising, falling, both) in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Detecting a rising edge output

What is the output of the rising_edge_detected signal after the clock cycle when signal_in changes from 0 to 1?

Verilog

module edge_detector(
  input wire clk,
  input wire signal_in,
  output reg rising_edge_detected
);
  reg signal_in_d;
  always @(posedge clk) begin
    signal_in_d <= signal_in;
    rising_edge_detected <= signal_in & ~signal_in_d;
  end
endmodule

A rising_edge_detected is 1 for one clock cycle after signal_in changes from 0 to 1

B rising_edge_detected is 1 when signal_in changes from 1 to 0

C rising_edge_detected stays 1 as long as signal_in is 1

D rising_edge_detected never becomes 1

💡 Hint

Think about how the delayed signal_in_d helps detect the rising edge.

The code stores the previous value of signal_in in signal_in_d. The expression signal_in & ~signal_in_d is true only when signal_in is 1 and the previous value was 0, which means a rising edge happened.

❓ Predict Output

intermediate

Detecting a falling edge output

What is the value of falling_edge_detected after the clock cycle when signal_in changes from 1 to 0?

Verilog

module edge_detector(
  input wire clk,
  input wire signal_in,
  output reg falling_edge_detected
);
  reg signal_in_d;
  always @(posedge clk) begin
    signal_in_d <= signal_in;
    falling_edge_detected <= ~signal_in & signal_in_d;
  end
endmodule

A falling_edge_detected never becomes 1

B falling_edge_detected stays 1 as long as signal_in is 0

C falling_edge_detected is 1 when signal_in changes from 0 to 1

D falling_edge_detected is 1 for one clock cycle after signal_in changes from 1 to 0

💡 Hint

Look at how the delayed signal_in_d is used with the inverted signal_in.

The expression ~signal_in & signal_in_d is true only when signal_in is 0 and the previous value was 1, indicating a falling edge.

❓ Predict Output

advanced

Detecting both rising and falling edges

What is the output of edge_detected signal when signal_in changes from 0 to 1 or from 1 to 0?

Verilog

module edge_detector(
  input wire clk,
  input wire signal_in,
  output reg edge_detected
);
  reg signal_in_d;
  always @(posedge clk) begin
    signal_in_d <= signal_in;
    edge_detected <= signal_in ^ signal_in_d;
  end
endmodule

A edge_detected is 1 only after rising edges

B edge_detected is 1 for one clock cycle after any change in signal_in

C edge_detected is 1 only after falling edges

D edge_detected never becomes 1

💡 Hint

XOR (^) is true when inputs differ.

The XOR of current and previous signal_in is 1 when signal_in changes value, so edge_detected is 1 for one clock cycle after any edge.

🧠 Conceptual

advanced

Understanding edge detection timing

Why does the edge detector use a delayed version of signal_in (like signal_in_d) to detect edges?

A To synchronize the signal with the clock frequency

B To filter out noise from the input signal

C To compare the current and previous values of the signal and detect changes

D To invert the input signal for edge detection

💡 Hint

Think about how you know if a signal changed from one moment to the next.

By storing the previous value, the circuit can compare it with the current value to see if the signal changed, which means an edge happened.

🔧 Debug

expert

Identify the error in this edge detector code

What error will this Verilog code cause when synthesizing an edge detector for rising edges?

Verilog

module edge_detector(
  input wire clk,
  input wire signal_in,
  output reg rising_edge_detected
);
  reg signal_in_d;
  always @(posedge clk) begin
    signal_in_d <= signal_in;
    rising_edge_detected = signal_in & ~signal_in_d;
  end
endmodule

A Using blocking assignment (=) inside an always @(posedge clk) block causes incorrect behavior

B Missing sensitivity to signal_in in the always block

C signal_in_d is not initialized

D The output rising_edge_detected should be wire, not reg

💡 Hint

Consider the difference between blocking (=) and non-blocking (<=) assignments in sequential logic.

Inside a clocked always block, non-blocking assignments (<=) must be used to ensure correct timing and behavior. Using blocking assignment (=) can cause race conditions and incorrect simulation/synthesis results.

Practice

1. What does a rising edge detector in Verilog detect?
always @(posedge clk) is often used in such detectors.

easy

A. Both 0 to 1 and 1 to 0 changes

B. A change of signal from 1 to 0

C. A change of signal from 0 to 1

D. No change in signal

Solution

1. Step 1: Understand rising edge meaning

   A rising edge means the signal changes from low (0) to high (1).

2. Step 2: Relate to Verilog edge detection

   The posedge keyword triggers on this rising edge.

3. Final Answer:

   A change of signal from 0 to 1 -> Option C

4. Quick Check:

   Rising edge = 0 to 1 transition [OK]

Hint: Rising edge means signal goes from 0 to 1 [OK]

Common Mistakes:

• Confusing rising edge with falling edge
• Thinking it detects no change
• Mixing up posedge and negedge keywords

2. Which of the following Verilog code snippets correctly detects a falling edge of signal sig?

easy

A. always @(negedge sig) begin // detect falling edge end

B. always @(posedge sig) begin // detect falling edge end

C. always @(sig) begin // detect falling edge end

D. always @(posedge clk) if (sig == 1) // detect falling edge

Solution

1. Step 1: Identify falling edge keyword

   Falling edge detection uses negedge in Verilog.

2. Step 2: Match code to falling edge

   always @(negedge sig) begin // detect falling edge end uses always @(negedge sig), which triggers on signal going from 1 to 0.

3. Final Answer:

   always @(negedge sig) begin // detect falling edge end -> Option A

4. Quick Check:

   Falling edge = negedge keyword [OK]

Hint: Use negedge to detect falling edges in Verilog [OK]

Common Mistakes:

• Using posedge for falling edge detection
• Using level-sensitive sensitivity list
• Confusing signal and clock edges

3. Given this Verilog code snippet for detecting both edges of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire edge_detect = sig ^ sig_d;

What is the value of edge_detect when sig changes from 0 to 1?

medium

A. 1

B. 0

C. Undefined (X)

D. Remains previous value

Solution

1. Step 1: Understand delayed signal sig_d

   sig_d holds previous clock cycle's sig value.

2. Step 2: Calculate XOR for edge detection

   When sig changes from 0 to 1, XOR with previous 0 gives 1, indicating an edge.

3. Final Answer:

   1 -> Option A

4. Quick Check:

   sig ^ sig_d = 1 on edge [OK]

Hint: XOR current and delayed signal to detect edges [OK]

Common Mistakes:

• Forgetting to delay signal before XOR
• Assuming edge_detect stays 0 on change
• Confusing XOR with AND or OR

4. Identify the error in this Verilog code intended to detect a rising edge of sig:

reg sig_d;
always @(posedge clk) begin
  sig_d <= sig;
end
wire rising_edge = sig & ~sig_d;

medium

A. Using blocking assignment instead of non-blocking

B. Incorrect logic for rising edge detection

C. No sensitivity list for wire rising_edge

D. Missing initial value for sig_d

Solution

1. Step 1: Analyze rising edge logic

   Rising edge is when signal changes from 0 to 1, so previous was 0 and current is 1.

2. Step 2: Check given logic expression

   The expression sig & ~sig_d correctly detects rising edge by current high and previous low.

3. Step 3: Re-examine for errors

   Actually, the logic is correct; the error is elsewhere.

4. Step 4: Identify actual error

   Missing initial value for sig_d can cause unknown behavior at start.

5. Final Answer:

   Missing initial value for sig_d -> Option D

6. Quick Check:

   Initialize delayed signal to avoid unknowns [OK]

Hint: Initialize delayed signals to avoid unknown start values [OK]

Common Mistakes:

• Assuming logic expression is wrong
• Ignoring initial values for registers
• Confusing blocking and non-blocking assignments

5. You want to design a Verilog module that outputs a pulse of 1 clock cycle width whenever sig changes either from 0 to 1 or 1 to 0. Which code snippet correctly implements this?

hard

A. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig & ~sig_d;

B. reg sig_d;
always @(posedge clk) sig_d <= sig;
wire edge_pulse = sig ^ sig_d;

C. wire edge_pulse = (sig == 1) ? 1 : 0;

D. always @(posedge sig) edge_pulse = 1;

Solution

1. Step 1: Understand requirement for both edges

   The pulse should be high for one clock cycle on any signal change (rising or falling).

2. Step 2: Analyze each option

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; uses XOR between current and delayed signal, which is 1 only on change, producing a 1-cycle pulse.

3. Step 3: Confirm other options

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig & ~sig_d; detects only rising edge; C is level detection; D triggers on posedge of sig, not clock, and lacks pulse width control.

4. Final Answer:

   reg sig_d; always @(posedge clk) sig_d <= sig; wire edge_pulse = sig ^ sig_d; -> Option B

5. Quick Check:

   XOR current and delayed signal for both edges pulse [OK]

Hint: XOR current and delayed signals for both edges pulse [OK]

Common Mistakes:

• Using only rising edge logic for both edges
• Triggering on signal edge instead of clock
• Not producing single clock cycle pulse