Reset strategy (sync vs async) in Verilog - Visual Side-by-Side Comparison

Concept Flow - Reset strategy (sync vs async)

Start

↓

Reset signal asserted?

No→Normal operation

Yes↓

Synchronous Reset?

Yes→Reset applied on clock edge

↓

Asynchronous Reset applied immediately

↓

Reset released?

No→Hold reset state

Yes↓

Resume normal operation

The reset strategy decides when and how the reset signal affects the circuit: synchronous resets act on clock edges, asynchronous resets act immediately.

Execution Sample

Verilog

always @(posedge clk or posedge async_reset) begin
  if (async_reset)
    q <= 0;
  else
    q <= d;
end

This code shows an asynchronous reset that clears 'q' immediately when asserted, otherwise 'q' follows 'd' on clock edges.

Execution Table

Step	clk	async_reset	Condition	Action	q (output)
1	0	0	async_reset=0, posedge clk? No	No change	initial (unknown)
2	1 (rising)	0	async_reset=0, posedge clk=Yes	q <= d (assume d=1)	1
3	1	1 (rising)	async_reset=1 posedge async_reset=Yes	q <= 0 (reset)	0
4	0	1	async_reset=1, no clk edge	Hold reset	0
5	1 (rising)	0 (falling)	async_reset=0, posedge clk=Yes	q <= d (assume d=0)	0
6	0	0	No edges, no reset	No change	0

💡 Simulation ends after normal operation resumes with no reset asserted.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	Final
clk	0	1	1	0	1	0	0
async_reset	0	0	1	1	1	0	0
q	X	X	1	0	0	0	0
d	Assumed	1	1	1	1	0	0

Key Moments - 3 Insights

Why does 'q' reset immediately when async_reset goes high, even if clk doesn't change?

Because the always block triggers on posedge async_reset, the reset happens immediately without waiting for clk edge (see execution_table step 3).

What happens if reset is synchronous and asserted just before clk rising edge?

The reset only affects 'q' at the next clk rising edge, so 'q' changes on that clock edge, not immediately (not shown here but implied by sync reset behavior).

Why does 'q' hold its reset value when async_reset stays high and clk toggles?

Because async_reset is still asserted, the reset condition dominates and 'q' stays at 0 regardless of clk edges (see step 4).

Visual Quiz - 3 Questions

Look at the execution_table at step 3, what causes 'q' to reset to 0?

A posedge clk

B async_reset falling edge

C posedge async_reset

D No signal change

💡 Hint

Check the 'Condition' column at step 3 showing posedge async_reset triggers reset.

At which step does 'q' first take the value of 'd' after reset is released?

A Step 3

B Step 5

C Step 2

D Step 6

💡 Hint

Look at step 5 where async_reset is 0 and posedge clk occurs, 'q' follows 'd'.

If async_reset was replaced by a synchronous reset, how would step 3 change?

A 'q' resets only at next posedge clk

B 'q' resets immediately at async_reset posedge

C 'q' never resets

D 'q' resets at negedge clk

💡 Hint

Synchronous reset acts only on clock edges, so reset waits for posedge clk.

Concept Snapshot

Reset Strategy in Verilog:
- Asynchronous reset triggers immediately on reset signal change.
- Synchronous reset triggers only on clock edge.
- Use 'or posedge async_reset' for async reset in always block.
- Use only 'posedge clk' for sync reset.
- Async reset can cause immediate reset; sync reset waits for clock.
- Choose reset type based on design needs and timing.

Full Transcript

This visual trace shows how reset signals affect a Verilog register 'q'. When async_reset goes high, 'q' resets immediately regardless of clock. When async_reset is low, 'q' updates on clock rising edge to follow 'd'. The flow diagram shows decision points: reset asserted? sync or async? reset applied accordingly. The execution table steps through clock and reset signals, showing 'q' changes. Variable tracker records signal values over time. Key moments clarify why async reset acts immediately and sync reset waits for clock. The quiz tests understanding of reset timing and effects. The snapshot summarizes reset strategies in Verilog.

Practice

1. What is the main difference between a synchronous reset and an asynchronous reset in Verilog?

easy

A. Synchronous reset is triggered by the clock edge, asynchronous reset works immediately.

B. Synchronous reset works immediately, asynchronous reset waits for the clock edge.

C. Both resets work only on the clock's rising edge.

D. Asynchronous reset requires a clock, synchronous reset does not.

Solution

1. Step 1: Understand synchronous reset behavior

   Synchronous reset activates only on the clock edge, so the reset signal is sampled with the clock.

2. Step 2: Understand asynchronous reset behavior

   Asynchronous reset activates immediately when asserted, independent of the clock.

3. Final Answer:

   Synchronous reset is triggered by the clock edge, asynchronous reset works immediately. -> Option A

4. Quick Check:

   Reset timing difference = synchronous on clock, async immediate [OK]

Hint: Sync reset waits clock, async reset acts immediately [OK]

Common Mistakes:

• Confusing which reset depends on clock
• Thinking async reset waits for clock edge
• Assuming both resets behave the same

2. Which of the following is the correct Verilog syntax for a synchronous reset inside an always block?

easy

A. always @(posedge clk or posedge rst) begin if (rst) q <= 0; else q <= d; end

B. always @(posedge clk) begin if (rst) q <= 0; else q <= d; end

C. always @(rst) begin if (rst) q <= 0; else q <= d; end

D. always @(negedge rst) begin q <= 0; end

Solution

1. Step 1: Identify synchronous reset syntax

   Synchronous reset is checked inside a clock-only sensitivity list, typically @(posedge clk).

2. Step 2: Check reset condition inside the block

   The reset condition is inside the always block, using if (rst) to reset synchronously.

3. Final Answer:

   always @(posedge clk) begin if (rst) q <= 0; else q <= d; end -> Option B

4. Quick Check:

   Sync reset inside clock-only always block [OK]

Hint: Sync reset inside clock-only always block [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Using asynchronous sensitivity list for sync reset
• Missing clock edge in always block

3. Given the following Verilog code, what will be the value of q after the asynchronous reset rst is deasserted?

reg q;
always @(posedge clk or posedge rst) begin
  if (rst) q <= 1'b0;
  else q <= d;
end

medium

A. q will immediately reset to 0 when rst is asserted, then follow d on clock edges.

B. q will reset to 0 only on the next clock edge after rst is asserted.

C. q will never reset because rst is asynchronous.

D. q will hold its previous value regardless of rst.

Solution

1. Step 1: Analyze asynchronous reset sensitivity

   The always block triggers on posedge clk or posedge rst, so when rst is asserted, q resets immediately.

2. Step 2: Behavior after reset deassertion

   After rst is deasserted, q updates on clock edges following the value of d.

3. Final Answer:

   q will immediately reset to 0 when rst is asserted, then follow d on clock edges. -> Option A

4. Quick Check:

   Async reset immediate, then sync update [OK]

Hint: Async reset triggers immediately, sync updates after [OK]

Common Mistakes:

• Thinking async reset waits for clock edge
• Assuming q holds value during reset
• Confusing reset assertion and deassertion timing

4. Identify the error in this Verilog code snippet implementing a synchronous reset:

always @(posedge clk or posedge rst) begin
  if (rst) q <= 0;
  else q <= d;
end

medium

A. The assignment operator should be = instead of <=.

B. The reset condition should be checked outside the always block.

C. The clock edge should be negedge instead of posedge.

D. The reset should not be in the sensitivity list for synchronous reset.

Solution

1. Step 1: Check sensitivity list for synchronous reset

   Synchronous reset should only be sensitive to the clock edge, not the reset signal.

2. Step 2: Identify the error

   Including posedge rst makes the reset asynchronous, which contradicts the synchronous reset intent.

3. Final Answer:

   The reset should not be in the sensitivity list for synchronous reset. -> Option D

4. Quick Check:

   Sync reset sensitivity = clock only [OK]

Hint: Sync reset sensitivity list excludes reset signal [OK]

Common Mistakes:

• Including reset in sensitivity list for sync reset
• Misunderstanding sensitivity list purpose
• Using blocking assignment instead of non-blocking

5. You need to design a flip-flop with a reset that must clear the output immediately when asserted, but also synchronize with the clock to avoid metastability issues. Which reset strategy is best and how should it be implemented?

hard

A. Use an asynchronous reset without synchronization.

B. Use a synchronous reset only, ignoring immediate reset requirement.

C. Use an asynchronous reset with a synchronizer circuit on the reset signal.

D. Use two separate resets: one async and one sync, both controlling the flip-flop.

Solution

1. Step 1: Understand immediate reset need

   Immediate clearing requires asynchronous reset to react without waiting for clock.

2. Step 2: Avoid metastability by synchronizing reset

   To prevent metastability, the asynchronous reset signal should be passed through synchronizer flip-flops before use.

3. Step 3: Combine both requirements

   Using async reset with synchronizer achieves immediate reset and safe clock domain crossing.

4. Final Answer:

   Use an asynchronous reset with a synchronizer circuit on the reset signal. -> Option C

5. Quick Check:

   Async reset + synchronizer = immediate and safe reset [OK]

Hint: Async reset plus synchronizer avoids metastability [OK]

Common Mistakes:

• Using only synchronous reset ignoring immediate reset
• Using async reset without synchronization causing metastability
• Trying to use two resets on same flip-flop incorrectly